Victor V. Zyuban
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
14
Venues
6
Active years
1998–2013
Best venue rank
A*
Where they publish
Papers
14 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2013 | ICCAD | Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis. | Nagu R. Dhanwada, David J. Hathaway, Victor V. Zyuban, Peng Peng, Karl Moody, William W. Dungan, Arun Joseph, Rahul M. Rao, Christopher J. Gonzalez |
| 2013 | ISLPED | Power reduction by aggressive synthesis design space exploration. | Matthew M. Ziegler, George Gristede, Victor V. Zyuban |
| 2009 | ISLPED | The opportunity cost of low power design: a case study in circuit tuning. | Matthew M. Ziegler, Victor V. Zyuban, George Gristede, Milena Vratonjic, Joshua Friedrich |
| 2008 | ISCA | A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime. | Jeonghee Shin, Victor V. Zyuban, Pradip Bose, Timothy Mark Pinkston |
| 2007 | DSN | A Framework for Architecture-Level Lifetime Reliability Modeling. | Jeonghee Shin, Victor V. Zyuban, Zhigang Hu, Jude A. Rivers, Pradip Bose |
| 2005 | HPCA | Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. | Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler |
| 2005 | ISCA | Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling. | Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen |
| 2004 | ISLPED | Microarchitectural techniques for power gating of execution units. | Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose |
| 2002 | ISLPED | Low power integrated scan-retention mechanism. | Victor V. Zyuban, Stephen V. Kosonocky |
| 2002 | ISLPED | Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels. | Victor V. Zyuban, Philip N. Strenski |
| 2002 | MICRO | Optimizing pipelines for power and performance. | Viji Srinivasan, David M. Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma |
| 2001 | ISLPED | Clocking strategies and scannable latches for low power appliacations. | Victor V. Zyuban, David Meltzer |
| 2000 | ISLPED | Optimization of high-performance superscalar architectures for energy efficiency. | Victor V. Zyuban, Peter M. Kogge |
| 1998 | ISLPED | The energy complexity of register files. | Victor V. Zyuban, Peter M. Kogge |