Vidyasagar Nookala
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
4
Active years
2004–2006
Best venue rank
A*
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2006 | ISLPED | Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis. | Vidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar |
| 2006 | ISPASS | Comparing simulation techniques for microarchitecture-aware floorplanning. | Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar |
| 2005 | DAC | Microarchitecture-aware floorplanning using a statistical design of experiments approach. | Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar |
| 2005 | DAC | Robust gate sizing by geometric programming. | Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, Sachin S. Sapatnekar |
| 2005 | ISCAS | Designing optimized pipelined global interconnects: algorithms and methodology impact. | Vidyasagar Nookala, Sachin S. Sapatnekar |
| 2004 | DAC | A method for correcting the functionality of a wire-pipelined circuit. | Vidyasagar Nookala, Sachin S. Sapatnekar |