Vijay Raghunat
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2006–2006
Best venue rank
A
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2006 | ISLPED | An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. | Yan Lin, Yu Hu, Lei He, Vijay Raghunat |