Vijay Shankar Pasupureddi
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
1
Active years
2024–2025
Best venue rank
C
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ISCAS | Breaking the Trade-off Between Input Impedance and Mixer Paths in Sub-Harmonic N-Path Mixer-First RF Front-end. | Raviteja Kammari, Vijay Shankar Pasupureddi |
| 2025 | ISCAS | A ±0.6 dB, 256-μW Digital-Intensive RSSI with 80-dB Dynamic-Range in 65-nm CMOS. | Sivaiah Naali, Ravi Prakash Bisen, Raviteja Kammari, Vijay Shankar Pasupureddi |
| 2025 | ISCAS | 350-fJ/spike, 30-Hz Bio-inspired Silicon Neuron Circuit in 0.2 V, 65 nm CMOS. | Sivaiah Naali, Srikanth Vuppunuthala, Vijay Shankar Pasupureddi |
| 2024 | ISCAS | A 0.2 pJ/bit, Energy-Efficient, Half-Rate Hybrid Circuit Topology at 6-Gb/s in 1.2V, 65 nm CMOS. | Prema Kumar Govindaswamy, Mursina Khatun, Vijay Shankar Pasupureddi |
| 2024 | ISCAS | A 2 | Prema Kumar Govindaswamy, Mursina Khatun, Vijay Shankar Pasupureddi |
| 2024 | ISCAS | A 15-Gb/s, 0.036 pJ/bit, Half-Rate, Low Power PRBS Generator in 1.2 V, 65 nm CMOS. | Perakalapudi Ravibabu, Prema Kumar Govindaswamy, Vijay Shankar Pasupureddi |