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Vijaya Sankara Rao Pasupureddi

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

13

Venues

2

Active years

2008–2022

Best venue rank

C

Where they publish

Papers

13 indexed papers, newest first.

YearVenueTitleAuthors
2022ISCASPower Efficient Echo-Cancellation Based Hybrid for Full-Duplex Chip-to-Chip Interconnects.Prema Kumar Govindaswamy, Nijwm Wary, Vijaya Sankara Rao Pasupureddi
2022ISCASA Low-Power Half-Rate Charge-Steering Hybrid for Full-Duplex Chip-to-Chip Interconnects.Prema Kumar Govindaswamy, Nijwm Wary, Vijaya Sankara Rao Pasupureddi
2021ISCASA Process Scalable Architecture for Low Noise Figure Sub-Sampling Mixer-First RF Front-End.Rakesh Rena, Suraj Kumar Verma, Vijaya Sankara Rao Pasupureddi
2020ISCASAn Adaptive Hybrid with Residue Monitor for Full-Duplex On-Chip Interconnects.Pankaj Venuturupalli, Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi
2016ISCASA new hybrid circuit topology for simultaneous bidirectional signaling over on-chip interconnects.Divya Duvvuri, Somanshu Agarwal, Vijaya Sankara Rao Pasupureddi
2016ISCASA low power charge mode compressive acquisition of multichannel EEG signals.Bhuvanan Kaliannan, Vijaya Sankara Rao Pasupureddi
2015ISCASMIL-STD-1553+: Integrated remote terminal and bus controller at 100-Mb/s data rate.Prateek Pendyala, Vijaya Sankara Rao Pasupureddi
2014VLSIDA Power Efficient Fully Differential Back Terminated Current-Mode HDMI Source.R. Gopikrishnan, Vijaya Sankara Rao Pasupureddi, Govindarajulu Regeti
2014VLSIDA Low Power CMOS Imager Based on Distributed Compressed Sensing.Bhuvanan Kaliannan, Vijaya Sankara Rao Pasupureddi
2013ISCASA low-power area-efficient compressive sensing approach for multi-channel neural recording.Mahsa Shoaran, Mariazel Maqueda Lopez, Vijaya Sankara Rao Pasupureddi, Yusuf Leblebici, Alexandre Schmid
2013VLSIDImplementation of a Charge Redistribution Based 2-D DCT Architecture for Wireless Capsule Endoscopy.Bhuvanan Kaliannan, Vijaya Sankara Rao Pasupureddi
2011VLSIDA New Double Data Rate(DDR) Dual-Mode Duobinary Transmitter Architecture.Mrigank Sharad, Vijaya Sankara Rao Pasupureddi, Pradip Mandal
2008VLSIDExploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design.T. Venkata Kalyan, Madhu Mutyam, Vijaya Sankara Rao Pasupureddi