Vili Viitamki
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
2017–2018
Best venue rank
C
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | DSD | Feasibility of FPGA Accelerated IPsec on Cloud. | Markku Vajaranta, Vili Viitamki, Arto Oinonen, Timo D. Hmlinen, Ari Kulmala, Jouni Markunmki |
| 2018 | ISCAS | FPGA-Powered 4K120p HEVC Intra Encoder. | Panu Sjvall, Vili Viitamki, Jarno Vanne, Timo D. Hmlinen, Ari Kulmala |
| 2018 | ISCAS | Live Demonstration: 4K100p HEVC Intra Encoder. | Vili Viitamki, Panu Sjvall, Jarno Vanne, Timo D. Hmlinen, Ari Kulmala |
| 2017 | ICASSP | High-level synthesis implementation of HEVC 2-D DCT/DST on FPGA. | Panu Sjovall, Vili Viitamki, Jarno Vanne, Timo D. Hmlinen |
| 2017 | ISCAS | High-level synthesized 2-D IDCT/IDST implementation for HEVC codecs on FPGA. | Vili Viitamki, Panu Sjovall, Jarno Vanne, Timo D. Hmlinen |