| 2025 | VLSID | Layer-Specific Hardware Pooling Designs for CNN Accelerators. | Vinay Rayapati, Mahati Basavaraju, Madhav Rao |
| 2024 | ISCAS | POCO: Hardware Characterization of Activation Functions using POSIT-CORDIC Architecture. | Mahati Basavaraju, Vinay Rayapati, Madhav Rao |
| 2024 | ISCAS | VPU-CIM: A 130nm, 33.98 TOPS/W RRAM based Compute-In-Memory Vector Co-Processor. | J. Chithambara Moorthii, Vinay Rayapati, Nanditha Rao, Manan Suri |
| 2024 | ISCAS | FPGA-based Hardware Software Co-design to Accelerate Brain Tumour Segmentation. | Vinay Rayapati, Gogireddy Ravi Kiran Reddy, Gandi Ajay Kumar, Saketh Gajawada, Sanampudi Gopala Krishna Reddy, Nanditha Rao |
| 2024 | VLSID | EBACA: Efficient Bfloat16-based Activation Function Implementation Using Enhanced CORDIC Architecture. | Vinay Rayapati, Sanampudi Gopala Krishna Reddy, Gandi Ajay Kumar, Gogireddy Ravi Kiran Reddy, Madhav Rao |
| 2023 | DSD | High Performance and Energy Efficient AMD and BWAD Pooling Schemes Characterised for CNN Accelerators. | Vinay Rayapati, Mahati Basavaraju, Madhav Rao |