Vinay Saripalli
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
2010–2024
Best venue rank
A*
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2024 | DAC | CDLS: Constraint Driven Generative AI Framework for Analog Layout Synthesis. | Prasanth Mangalagiri, Lynn Qian, Farrukh Zafar, Praveen Mosalikanti, Phoebe Chang, Arun Kurian, Vinay Saripalli |
| 2012 | ISLPED | Design space exploration of workload-specific last-level caches. | Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir |
| 2011 | DAC | An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores. | Vinay Saripalli, Asit K. Mishra, Suman Datta, Vijaykrishnan Narayanan |
| 2011 | ISLPED | Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores. | Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta |
| 2010 | VLSID | Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors. | Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta |