Vinod Ganesan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
2
Active years
2020–2026
Best venue rank
A
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | VLSID | A 8-16 Gb/s/pin Full-Duplex Voltage-Mode Transmitter with Pulse Width Modulation Based Equalization and Analog Echo Canceller. | Saurabh Saxena, Vinod Ganesan, Shubham Choudhary |
| 2021 | DATE | Seclusive Cache Hierarchy for Mitigating Cross-Core Cache and Coherence Directory Attacks. | Vishal Gupta, Vinod Ganesan, Biswabandan Panda |
| 2021 | DATE | FuSeConv: Fully Separable Convolutions for Fast Inference on Systolic Arrays. | Surya Selvam, Vinod Ganesan, Pratyush Kumar |
| 2020 | DATE | Sparsity-Aware Caches to Accelerate Deep Neural Networks. | Vinod Ganesan, Sanchari Sen, Pratyush Kumar, Neel Gala, Kamakoti Veezhinathan, Anand Raghunathan |