Vivian Desalphine
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
1
Active years
2020–2026
Best venue rank
National
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | VLSID | BHARAT-TPM: Micro-Architecture Design of Scalable Hardware Random Number Generator for a RISC-V Trusted Platform Module. | Soumya G. Hosmani, Raja Sekar K, Aneesh Raveendran, Vivian Desalphine, Haribabu P, S. D. Sudarsan |
| 2023 | VLSID | Design and Analysis of Posit Quire Processing Engine for Neural Network Applications. | Pranose J. Edavoor, Aneesh Raveendran, David Selvakumar, Vivian Desalphine, Shankar G. Dharani, Gopal Raut |
| 2021 | VLSID | P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor. | Sandra Jean, Aneesh Raveendran, A. David Selvakumar, Gagandeep Kaur, Shankar G. Dharani, Shashikala Gunderao Pattanshetty, Vivian Desalphine |
| 2021 | VLSID | PositGen-A Verification Suite for Posit Arithmetic. | Annarao Kulkarni, Shashikala Gunderao Pattanshetty, Aneesh Raveendran, David Selvakumar, Sandra Jean, Vivian Desalphine |
| 2020 | VLSID | A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture. | Aneesh Raveendran, Sandra Jean, J. Mervin, Vivian Desalphine, David Selvakumar |