| 2026 | ASPDAC | UltraMalloc: Efficient FPGA-based Memory Allocation Framework Optimized for HBM. | Yuwei Qu, Yiqing Mao, Yanxing Jin, Wai-Shing Luk, Lingli Wang |
| 2026 | ASPDAC | Novel Multi-Corner Delay Padding using Path Relationship Analysis and Dual Decomposition. | Kaixiang Zhu, Jiangnan Li, Lingli Wang, Wai-Shing Luk |
| 2026 | DATE | Compacted-LUT: Fine-Grained Customizable LUT Architecture via SRAM-MUX Co-Optimization. | Mingyang Chen, Yunfei Dai, Wai-Shing Luk, Qing He, Yu He, Lingli Wang |
| 2026 | ISCA | Lora: Towards Improved Applicability of Reconfigurable Architecture for Versatile Nonlinear Functions. | Yuan Dai, Guibin Zou, Yuanda Yang, Huan Lin, Jiahang Lou, Yiwen Luo, Xinyu Cai, Wenbo Yin, Wai-Shing Luk, Lingli Wang |
| 2025 | ASPDAC | Towards Efficient Data Parallelism on Spatial CGRA via Constraint Satisfaction and Graph Coloring. | Yuan Dai, Xuchen Gao, Chen Shen, Bingbing Peng, Wenbo Yin, Wai-Shing Luk, Lingli Wang |
| 2025 | ASPDAC | Yield-driven Clock Skew Scheduling Based on Generalized Extreme Value Distribution. | Kaixiang Zhu, Wai-Shing Luk, Lingli Wang |
| 2024 | FPL | CFEACT: A CGRA-based Framework Enabling Agile CNN and Transformer Accelerator Design. | Yiqing Mao, Xuchen Gao, Jiahang Lou, Yunhui Qiu, Wenbo Yin, Wai-Shing Luk, Lingli Wang |
| 2017 | ASPDAC | Network flow based cut redistribution and insertion for advanced 1D layout design. | Ye Zhang, Wai-Shing Luk, Fan Yang, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng |
| 2017 | ISCAS | Layout decomposition for hybrid E-beam and DSA double patterning lithography. | Yunfeng Yang, Fan Yang, Wai-Shing Luk, Changhao Yan, Xuan Zeng, Xiangdong Hu |
| 2015 | ASPDAC | Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography. | Yunfeng Yang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng, Dian Zhou |
| 2013 | ICCAD | Layout decomposition with pairwise coloring for multiple patterning lithography. | Ye Zhang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng |
| 2011 | DATE | An efficient algorithm for multi-domain clock skew scheduling. | Yanling Zhi, Wai-Shing Luk, Hai Zhou, Changhao Yan, Hengliang Zhu, Xuan Zeng |
| 2010 | ICCAD | Fast and lossless graph division method for layout decomposition using SPQR-tree. | Wai-Shing Luk, Huiping Huang |
| 2008 | DAC | Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays. | Yi Wang, Wai-Shing Luk, Xuan Zeng, Jun Tao, Changhao Yan, Jiarong Tong, Wei Cai, Jia Ni |
| 2007 | ASPDAC | Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic. | Xuexin Liu, Wai-Shing Luk, Yu Song, Pushan Tang, Xuan Zeng |
| 2007 | ASPDAC | WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design. | Peng Zhang, Wai-Shing Luk, Yu Song, Jiarong Tong, Pushan Tang, Xuan Zeng |
| 1997 | ICDCS | Two New Quorum Based Algorithms for Distributed Mutual Exclusion. | Wai-Shing Luk, Tien-Tsin Wong |