Walker J. Turner
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
2020–2025
Best venue rank
A*
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | DATE | ChipVQA: Benchmarking Visual Language Models for Chip Design. | Haoyu Yang, Qijing Huang, Nathaniel Ross Pinckney, Walker J. Turner, Wenfei Zhou, Yanqing Zhang, Chia-Tung Ho, Chen-Chia Chang, Haoxing Ren |
| 2022 | DATE | Routability-Aware Placement for Advanced FinFET Mixed-Signal Circuits using Satisfiability Modulo Theories. | Hao Chen, Walker J. Turner, David Z. Pan, Haoxing Ren |
| 2022 | ICCAD | TAG: Learning Circuit Spatial Embedding from Layouts. | Keren Zhu, Hao Chen, Walker J. Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Haoxing Ren |
| 2021 | DATE | Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization. | Mingjie Liu, Walker J. Turner, George F. Kokai, Brucek Khailany, David Z. Pan, Haoxing Ren |
| 2020 | DAC | ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks. | Haoxing Ren, George F. Kokai, Walker J. Turner, Ting-Sheng Ku |