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Warren A. Hunt Jr.

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

32

Venues

12

Active years

1987–2025

Best venue rank

A*

Where they publish

Papers

32 indexed papers, newest first.

YearVenueTitleAuthors
2025FMCADA Method for the Verification of Memory Management Software in the Presence of TLBs.Yahya Sohail, Warren A. Hunt Jr.
2024FMCADAutomatic Verification of Right-Greedy Numerical Linear Algebra Algorithms.Carl Kwan, Warren A. Hunt Jr.
2024ITPFormalizing the Cholesky Factorization Theorem.Carl Kwan, Warren A. Hunt Jr.
2017ACSSCHow to think about self-timed systems.Marly Roncken, Ivan E. Sutherland, Chris Chen, Yong Hei, Warren A. Hunt Jr., Cuong K. Chau, Swetha Mettala Gilla, Hoon Park, Xiaoyu Song, Anping He, Hong Chen
2017CADEEfficient Certified RAT Verification.Lus Cruz-Filipe, Marijn J. H. Heule, Warren A. Hunt Jr., Matt Kaufmann, Peter Schneider-Kamp
2017ITPEfficient, Verified Checking of Propositional Proofs.Marijn Heule, Warren A. Hunt Jr., Matt Kaufmann, Nathan Wetzler
2015CADEExpressing Symmetry Breaking in DRAT Proofs.Marijn Heule, Warren A. Hunt Jr., Nathan Wetzler
2014FMCADSimulation and formal verification of x86 machine-code programs that make system calls.Shilpi Goel, Warren A. Hunt Jr., Matt Kaufmann, Soumava Ghosh
2014SATDRAT-trim: Efficient Checking and Trimming Using Expressive Clausal Proofs.Nathan Wetzler, Marijn Heule, Warren A. Hunt Jr.
2013CADEVerifying Refutations with Extended Resolution.Marijn Heule, Warren A. Hunt Jr., Nathan Wetzler
2013FMCADTrimming while checking clausal proofs.Marijn Heule, Warren A. Hunt Jr., Nathan Wetzler
2013ITPA Parallelized Theorem Prover for a Logic with Parallel Execution.David L. Rager, Warren A. Hunt Jr., Matt Kaufmann
2013ITPMechanical Verification of SAT Refutations with Extended Resolution.Nathan Wetzler, Marijn Heule, Warren A. Hunt Jr.
2012FMCADA formal model of a large memory that supports efficient execution.Warren A. Hunt Jr., Matt Kaufmann
2011MEMOCODEA flexible formal verification framework for industrial scale validation.Anna Slobodov, Jared Davis, Sol Swords, Warren A. Hunt Jr.
2010FMCADVerifying VIA Nano microprocessor components.Warren A. Hunt Jr.
2010ISAIMUsing mathematics on an industrial scale.Warren A. Hunt Jr.
2010ITPA Mechanically Verified AIG-to-BDD Conversion Algorithm.Sol Swords, Warren A. Hunt Jr.
2009CAVCentaur Technology Media Unit Verification.Warren A. Hunt Jr., Sol Swords
2009FMCADConnecting pre-silicon and post-silicon verification.Sandip Ray, Warren A. Hunt Jr.
2008FMCADMechanized Information Flow Analysis through Inductive Assertions.Warren A. Hunt Jr., Robert Bellarmine Krug, Sandip Ray, William D. Young
2006CADEA SAT-Based Decision Procedure for the Subclass of Unrollable List Formulas in ACL2 (SULFA).Erik Reeber, Warren A. Hunt Jr.
2006DATEAutomatic insertion of low power annotations in RTL for pipelined microprocessors.Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt Jr.
2006FMCADAn Integration of HOL and ACL2.Michael J. C. Gordon, James Reynolds, Warren A. Hunt Jr., Matt Kaufmann
2005WABIA Compressed Format for Collections of Phylogenetic Trees and Improved Consensus Performance.Robert S. Boyer, Warren A. Hunt Jr., Serita M. Nelesen
2004CAVMechanical Mathematical Methods for Microprocessor Verification.Warren A. Hunt Jr.
2004CAVDeductive Verification of Pipelined Machines Using First-Order Quantification.Sandip Ray, Warren A. Hunt Jr.
2000FMCADHardware Modeling Using Function Encapsulation.Jun Sawada, Warren A. Hunt Jr.
1998CAVProcessor Verification with Precise Exeptions and Speculative Execution.Jun Sawada, Warren A. Hunt Jr.
1997CAVTrace Table Based Approach for Pipeline Microprocessor Verification.Jun Sawada, Warren A. Hunt Jr.
1997ICCDFormally Specifying and Mechanically Verifying Programs for the Motorola Complex Arithmetic Processor DSP.Bishop Brock, Warren A. Hunt Jr.
1987SPToward Verified Execution Environments.William R. Bevier, Warren A. Hunt Jr., William D. Young