Skip to content

Weigong Zhang

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

16

Venues

9

Active years

2016–2023

Best venue rank

A*

Where they publish

Papers

16 indexed papers, newest first.

YearVenueTitleAuthors
2023ICPADSA Bit Level Acceleration of Mixed Precision Neural Network.Dehui Qiu, Jing Wang, Yi Hou, Weigong Zhang, Lan Gao
2023ICPADSAccelerating Look-Up Table based Matrix Multiplication on GPUs.Yuchen Zhao, Lan Gao, Weigong Zhang, Jing Wang, Dehui Qiu
2022HPCCDAYuqi Bian, Jing Wang, Weigong Zhang, Lan Gao
2020HPCAEnabling Highly Efficient Capsule Networks Processing Through A PIM-Based Architecture Design.Xingyao Zhang, Shuaiwen Leon Song, Chenhao Xie, Jing Wang, Weigong Zhang, Xin Fu
2019ICA3PPReliability Enhancement of Neural Networks via Neuron-Level Vulnerability Quantization.Keyao Li, Jing Wang, Xin Fu, Xiufeng Sui, Weigong Zhang
2019ICA3PPNeuron Fault Tolerance Capability Based Computation Reuse in DNNs.Pengnian Qi, Jing Wang, Xiaoyan Zhu, Weigong Zhang
2019ICPADSEnabling Energy-Efficient and Reliable Neural Network via Neuron-Level Voltage Scaling.Shubo Liu, Xu Wang, Jing Wang, Xin Fu, Xingyao Zhang, Lan Gao, Weigong Zhang, Tao Li
2018HPCAIn-Situ AI: Towards Autonomous and Incremental Deep Learning for IoT Systems.Mingcong Song, Kan Zhong, Jiaqi Zhang, Yang Hu, Duo Liu, Weigong Zhang, Jing Wang, Tao Li
2018ICCDDR DRAM: Accelerating Memory-Read-Intensive Applications.Yuhai Cao, Chao Li, Quan Chen, Jingwen Leng, Minyi Guo, Jing Wang, Weigong Zhang
2017HPCAProcessing-in-Memory Enabled Graphics Processors for 3D Rendering.Chenhao Xie, Shuaiwen Leon Song, Jing Wang, Weigong Zhang, Xin Fu
2017ISORCExpected Completion Time Aware Message Scheduling for UM-BUS Interconnected System.Jiqin Zhou, Weigong Zhang, Keni Qiu, Ruiying Bai, Ying Wang, Xiaoyan Zhu
2016ICCDRefresh-aware loop scheduling for high performance low power volatile STT-RAM.Keni Qiu, Junpeng Luo, Zhiyao Gong, Weigong Zhang, Jing Wang, Yuanchao Xu, Tao Li, Chun Jason Xue
2016ICCDAn adaptive Non-Uniform Loop Tiling for DMA-based bulk data transfers on many-core processor.Keni Qiu, Yuanhui Ni, Weigong Zhang, Jing Wang, Xiaoqiang Wu, Chun Jason Xue, Tao Li
2016ICPPExploring Variation-Aware Fault-Tolerant Cache under Near-Threshold Computing.Jing Wang, Yanjun Liu, Weigong Zhang, Kezhong Lu, Keni Qiu, Xin Fu, Tao Li
2016MiddlewareUnderstanding the Behavior of Spark Workloads from Linux Kernel Parameters Perspective.Li Wang, Tianni Xu, Jing Wang, Weigong Zhang, Xiufeng Sui, Yungang Bao
2016SACBalanced loop retiming to effectively architect STT-RAM-based hybrid cache for VLIW processors.Keni Qiu, Weigong Zhang, Xiaoqiang Wu, Xiaoyan Zhu, Jing Wang, Yuanchao Xu, Chun Jason Xue