Wen-Pin Tu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
4
Active years
2010–2013
Best venue rank
B
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2013 | DATE | Co-synthesis of data paths and clock control paths for minimum-period clock gating. | Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng |
| 2013 | ICCAD | Low-power timing closure methodology for ultra-low voltage designs. | Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou |
| 2012 | ASPDAC | Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits. | Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng |
| 2012 | ISCAS | NBTI-aware dual threshold voltage assignment for leakage power reduction. | Wen-Pin Tu, Shih-Wei Wu, Shih-Hsu Huang, Mely Chen Chi |
| 2010 | ASPDAC | Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating. | Shih-Hsu Huang, Chia-Ming Chang, Wen-Pin Tu, Song-Bin Pan |