| 2025 | ASPDAC | AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. | Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang |
| 2025 | ASPDAC | A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks. | Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie |
| 2025 | ASPDAC | Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage. | Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Zhiyao Xie |
| 2025 | DAC | NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph. | Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, Zhiyao Xie |
| 2025 | DAC | ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis. | Wenkai Li, Yao Lu, Wenji Fang, Jing Wang, Qijun Zhang, Zhiyao Xie |
| 2025 | DAC | SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits. | Shang Liu, Jing Wang, Wenji Fang, Zhiyao Xie |
| 2025 | EMNLP | SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Models. | Shang Liu, Yao Lu, Wenji Fang, Jing Wang, Zhiyao Xie |
| 2025 | ICCAD | GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment. | Wenji Fang, Wang Jing, Yao Lu, Shang Liu, Zhiyao Xie |
| 2025 | ICLR | CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design. | Wenji Fang, Shang Liu, Jing Wang, Zhiyao Xie |
| 2025 | ISCA | Profile-Guided Temporal Prefetching. | Mengming Li, Qijun Zhang, Yichuan Gao, Wenji Fang, Yao Lu, Yongqing Ren, Zhiyao Xie |
| 2024 | DAC | Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. | Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie |
| 2024 | ICCAD | OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation. | Shang Liu, Yao Lu, Wenji Fang, Mengming Li, Zhiyao Xie |
| 2023 | ICCAD | MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. | Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie |
| 2023 | TACAS | WASIM: A Word-level Abstract Symbolic Simulation Framework for Hardware Formal Verification. | Wenji Fang, Hongce Zhang |