| 1990 | ITC | A multiple seed linear feedback shift register. | Jacob Savir, William H. McAnney |
| 1989 | ITC | Testing for Coupled Cells in Random-Access Memories. | Jacob Savir, William H. McAnney, Salvatore R. Vecchio |
| 1988 | ITC | Identification of Failing Tests with Cycling Registers. | Jacob Savir, William H. McAnney |
| 1986 | ITC | Built-In Checking of the Correct Self-Test Signature. | William H. McAnney, Jacob Savir |
| 1986 | ITC | Random Pattern Testability of Delay Faults. | Jacob Savir, William H. McAnney |
| 1985 | ITC | Self-Test of Random Access Memories. | Paul H. Bardell, William H. McAnney |
| 1985 | ITC | Random Pattern Testing for Data-Line Faults in an Embedded Multiport Memory. | Jacob Savir, William H. McAnney, Salvatore R. Vecchio |
| 1985 | ITC | Random Pattern Testing for Address-Line Faults in an Embedded Multiport Memory. | Jacob Savir, William H. McAnney, Salvatore R. Vecchio |
| 1984 | ITC | Parallel Pseudorandom Sequences for Built-In Test. | Paul H. Bardell, William H. McAnney |
| 1984 | ITC | Random Testing for Stuck-At Storage Cells in an Embedded Memory. | William H. McAnney, Paul H. Bardell, V. P. Gupta |
| 1982 | ITC | Self-Testing of Multichip Logic Modules. | Paul H. Bardell, William H. McAnney |