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William J. Dally

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

123

Venues

28

Active years

1985–2023

Best venue rank

A*

Where they publish

Papers

123 indexed papers, newest first.

YearVenueTitleAuthors
2023ASPLOSGPU-Initiated On-Demand High-Throughput Storage Access in the BaM System Architecture.Zaid Qureshi, Vikram Sharma Mailthody, Isaac Gelado, Seungwon Min, Amna Masood, Jeongmin Brian Park, Jinjun Xiong, Chris J. Newburn, Dmitri Vainbrand, I-Hsin Chung, Michael Garland, William J. Dally, Wen-Mei W. Hwu
2022ICMLOptimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training.Charbel Sakr, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, William J. Dally, Brucek Khailany
2021SPAASPAA'21 Panel Paper: Architecture-Friendly Algorithms versus Algorithm-Friendly Architectures.Guy E. Blelloch, William J. Dally, Margaret Martonosi, Uzi Vishkin, Katherine A. Yelick
2020HPCASpArch: Efficient Architecture for Sparse Matrix Multiplication.Zhekai Zhang, Hanrui Wang, Song Han, William J. Dally
2019DACAnalog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference.Angad S. Rekhi, Brian Zimmer, Nikola Nedovic, Ningxi Liu, Rangharajan Venkatesan, Miaorong Wang, Brucek Khailany, William J. Dally, C. Thomas Gray
2019HPCADarwin-WGA: A Co-processor Provides Increased Sensitivity in Whole Genome Alignments with High Speedup.Yatish Turakhia, Sneha D. Goenka, Gill Bejerano, William J. Dally
2019ICCADMAGNet: A Modular Accelerator Generator for Neural Networks.Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William J. Dally, Joel S. Emer, Stephen W. Keckler, Brucek Khailany
2019MICROSimba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture.Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler
2019USENIXDarwin: A Genomics Co-processor Provides up to 15, 000X Acceleration on Long Read Assembly.Yatish Turakhia, Gill Bejerano, William J. Dally
2018ASPLOSDarwin: A Genomics Co-processor Provides up to 15, 000X Acceleration on Long Read Assembly.Yatish Turakhia, Gill Bejerano, William J. Dally
2018DACBandwidth-efficient deep learning.Song Han, William J. Dally
2018ICLREfficient Sparse-Winograd Convolutional Neural Networks.Xingyu Liu, Jeff Pool, Song Han, William J. Dally
2017CVPRExploring the Granularity of Sparsity in Convolutional Neural Networks.Huizi Mao, Song Han, Jeff Pool, Wenshuo Li, Xingyu Liu, Yu Wang, William J. Dally
2017HPCAArchitecting an Energy-Efficient DRAM System for GPUs.Niladrish Chatterjee, Mike O'Connor, Donghyuk Lee, Daniel R. Johnson, Stephen W. Keckler, Minsoo Rhu, William J. Dally
2017ICLRDSD: Dense-Sparse-Dense Training for Deep Neural Networks.Song Han, Jeff Pool, Sharan Narang, Huizi Mao, Enhao Gong, Shijian Tang, Erich Elsen, Peter Vajda, Manohar Paluri, John Tran, Bryan Catanzaro, William J. Dally
2017ICLREfficient Sparse-Winograd Convolutional Neural Networks.Xingyu Liu, Song Han, Huizi Mao, William J. Dally
2017ICLRTrained Ternary Quantization.Chenzhuo Zhu, Song Han, Huizi Mao, William J. Dally
2017ISCASCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks.Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally
2017MICROFine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems.Mike O'Connor, Niladrish Chatterjee, Donghyuk Lee, John M. Wilson, Aditya Agrawal, Stephen W. Keckler, William J. Dally
2016ISCAEIE: Efficient Inference Engine on Compressed Deep Neural Network.Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally
2015ISCASLIP: reducing wire energy in the memory hierarchy.Subhasis Das, Tor M. Aamodt, William J. Dally
2015SCNetwork endpoint congestion control for fine-grained communication.Nan Jiang, Larry R. Dennison, William J. Dally
2014ICSAuthor retrospective for design tradeoffs for tiled CMP on-chip networks.William J. Dally, James D. Balfour
2014SCScaling the Power Wall: A Path to Exascale.Oreste Villa, Daniel R. Johnson, Mike O'Connor, Evgeny Bolotin, David W. Nellans, Justin Luitjens, Nikolai Sakharnykh, Peng Wang, Paulius Micikevicius, Anthony Scudiero, Stephen W. Keckler, William J. Dally
2013DAC21st century digital design tools.William J. Dally, Chris Malachowsky, Stephen W. Keckler
2013ISPASSA detailed and flexible cycle-accurate Network-on-Chip simulator.Nan Jiang, Daniel U. Becker, George Michelogiannakis, James D. Balfour, Brian Towles, David E. Shaw, John Kim, William J. Dally
2013SCChannel reservation protocol for over-subscribed channels and destinations.George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally
2012HPCANetwork congestion avoidance through Speculative Reservation.Nan Jiang, Daniel U. Becker, George Michelogiannakis, William J. Dally
2012ICCDAdaptive Backpressure: Efficient buffer management for on-chip networks.Daniel U. Becker, Nan Jiang, George Michelogiannakis, William J. Dally
2012MICROUnifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor.Mark Gebhart, Stephen W. Keckler, Brucek Khailany, Ronny Krashinsky, William J. Dally
2011ISCAEnergy-efficient mechanisms for managing thread context in throughput processors.Mark Gebhart, Daniel R. Johnson, David Tarjan, Stephen W. Keckler, William J. Dally, Erik Lindholm, Kevin Skadron
2011MICROA compile-time managed multi-level register file hierarchy.Mark Gebhart, Stephen W. Keckler, William J. Dally
2011MICROPacket chaining: efficient single-cycle allocation for on-chip networks.George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally
2010CASESFine-grain dynamic instruction placement for L0 scratch-pad memory.JongSoo Park, James D. Balfour, William J. Dally
2010ICPPBlock-Parallel Programming for Real-Time Embedded Applications.David Black-Schaffer, William J. Dally
2010ISCAMoving the needle, computer architecture research in academe and industry.William J. Dally
2010ICSThroughput computing.William J. Dally
2010SPAABuffer-space efficient and deadlock-free scheduling of stream applications on multi-core architectures.JongSoo Park, William J. Dally
2009HPCAElastic-buffer flow control for on-chip networks.George Michelogiannakis, James D. Balfour, William J. Dally
2009ISCAIndirect adaptive routing on large scale interconnection networks.Nan Jiang, John Kim, William J. Dally
2009SCAllocator implementations for network-on-chip routers.Daniel U. Becker, William J. Dally
2009SCRouter designs for elastic buffer on-chip networks.George Michelogiannakis, William J. Dally
2008EuroParStream Scheduling: A Framework to Manage Bulk Operations in Memory Hierarchies.Abhishek Das, William J. Dally
2008ISCATechnology-Driven, Highly-Scalable Dragonfly Topology.John Kim, William J. Dally, Steve Scott, Dennis Abts
2008PPoPPA portable runtime interface for multi-level memory hierarchies.Mike Houston, Ji Young Park, Manman Ren, Timothy J. Knight, Kayvon Fatahalian, Alex Aiken, William J. Dally, Pat Hanrahan
2007DATERegister pointer architecture for efficient embedded processors.JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally
2007HPCAInterconnect-Centric Computing.William J. Dally
2007ISCAFlattened butterfly: a cost-efficient topology for high-radix networks.John Kim, William J. Dally, Dennis Abts
2007ICSTradeoff between data-, instruction-, and thread-level parallelism in stream processors.Jung Ho Ahn, Mattan Erez, William J. Dally
2007ICSExecuting irregular scientific applications on stream architectures.Mattan Erez, Jung Ho Ahn, Jayanth Gummaraju, Mendel Rosenblum, William J. Dally
2007ISLPEDFuture of on-chip interconnection architectures.Shekhar Borkar, William J. Dally
2007MICROFlattened Butterfly Topology for On-Chip Networks.John Kim, James D. Balfour, William J. Dally
2007PPoPPCompilation for explicitly managed memory hierarchies.Timothy J. Knight, Ji Young Park, Manman Ren, Mike Houston, Mattan Erez, Kayvon Fatahalian, Alex Aiken, William J. Dally, Pat Hanrahan
2006ICCDComputer Architecture in the Many-Core Era.William J. Dally
2006ISCAThe BlackWidow High-Radix Clos Network.Steve Scott, Dennis Abts, John Kim, William J. Dally
2006ICSDesign tradeoffs for tiled CMP on-chip networks.James D. Balfour, William J. Dally
2006SCArchitecture - The design space of data-parallel memory systems.Jung Ho Ahn, Mattan Erez, William J. Dally
2006SCSequoia: programming the memory hierarchy.Kayvon Fatahalian, Daniel Reiter Horn, Timothy J. Knight, Larkhoon Leem, Mike Houston, Ji Young Park, Mattan Erez, Manman Ren, Alex Aiken, William J. Dally, Pat Hanrahan
2006SCInterconnect routing and scheduling - Adaptive routing in high-radix clos network.John Kim, William J. Dally, Dennis Abts
2006SCMulti-core issues - Multi-Core for HPC: breakthrough or breakdown?Thomas L. Sterling, Peter M. Kogge, William J. Dally, Steve Scott, William Gropp, David E. Keyes, Peter H. Beckman
2005DACExplaining the gap between ASIC and custom power: a custom perspective.Andrew Chang, William J. Dally
2005HPCAScatter-Add in Data Parallel Architectures.Jung Ho Ahn, Mattan Erez, William J. Dally
2005ISCAMicroarchitecture of a High-Radix Router.John Kim, William J. Dally, Brian Towles, Amit K. Gupta
2005SCFault Tolerance Techniques for the Merrimac Streaming Supercomputer.Mattan Erez, Nuwan Jayasena, Timothy J. Knight, William J. Dally
2004HPCAStream Register Files with Indexed Access.Nuwan Jayasena, Mattan Erez, Jung Ho Ahn, William J. Dally
2004ISCAEvaluating the Imagine Stream Architecture.Jung Ho Ahn, William J. Dally, Brucek Khailany, Ujval J. Kapasi, Abhishek Das
2004SCAnalysis and Performance Results of a Molecular Modeling Application on Merrimac.Mattan Erez, Jung Ho Ahn, Ankit Garg, William J. Dally, Eric Darve
2004SPAAAdaptive channel queue routing on k-ary n-cubes.Arjun Singh, William J. Dally, Amit K. Gupta, Brian Towles
2004WCAEThe case for broader computer architecture education: keynote address.William J. Dally
2003HPCAExploring the VLSI Scalability of Stream Processors.Brucek Khailany, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens, Brian Towles
2003ICCDCMOS High-Speed I/Os - Present and Future.Ming-Ju Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John W. Poulton
2003ISCAGOAL: A Load-Balanced Adaptive Routing Algorithm for Torus Networks.Arjun Singh, William J. Dally, Amit K. Gupta, Brian Towles
2003SCMerrimac: Supercomputing with Streams.William J. Dally, Francois Labonte, Abhishek Das, Pat Hanrahan, Jung Ho Ahn, Jayanth Gummaraju, Mattan Erez, Nuwan Jayasena, Ian Buck, Timothy J. Knight, Ujval J. Kapasi
2003SPAAThroughput-centric routing algorithm design.Brian Towles, William J. Dally, Stephen P. Boyd
2002HOTIScalable Opto-Electronic Network (SOENet).Amit K. Gupta, William J. Dally, Arjun Singh, Brian Towles
2002ICCDThe Imagine Stream Processor.Ujval J. Kapasi, William J. Dally, Scott Rixner, John D. Owens, Brucek Khailany
2002ICCDVLSI Design and Verification of the Imagine Processor.Brucek Khailany, William J. Dally, Andrew Chang, Ujval J. Kapasi, Jinyung Namkoong, Brian Towles
2002ICCDMedia Processing Applications on the Imagine Stream Processor.John D. Owens, Scott Rixner, Ujval J. Kapasi, Peter R. Mattson, Brian Towles, Ben Serebrin, William J. Dally
2002ICCDA Stream Processor Development Platform.Ben Serebrin, John D. Owens, Chen H. Chen, Stephen P. Crago, Ujval J. Kapasi, Peter R. Mattson, Jinyung Namkoong, Scott Rixner, William J. Dally
2002INFOCOMGuaranteed Scheduling for Switches with Configuration Overhead.Brian Towles, William J. Dally
2002SPAALocality-preserving randomized oblivious routing on torus networks.Arjun Singh, William J. Dally, Brian Towles, Amit K. Gupta
2002SPAAWorst-case traffic for oblivious routing functions.Brian Towles, William J. Dally
2001DACRoute Packets, Not Wires: On-Chip Interconnection Networks.William J. Dally, Brian Towles
2001HPCAA Delay Model and Speculative Architecture for Pipelined Routers.Li-Shiuan Peh, William J. Dally
2001ISCASMonolithic chaotic communications system.Patrick Chiang, William J. Dally, Ming-Ju Edward Lee
2000ASPLOSCommunication Scheduling.Peter R. Mattson, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens
2000DACThe role of custom design in ASIC Chips.William J. Dally, Andrew Chang
2000HPCAFlit-Reservation Flow Control.Li-Shiuan Peh, William J. Dally
2000HPCARegister Organization for Media Processing.Scott Rixner, William J. Dally, Brucek Khailany, Peter R. Mattson, Ujval J. Kapasi, John D. Owens
2000ISCASmart Memories: a modular reconfigurable architecture.Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, Mark Horowitz
2000ISCAMemory access scheduling.Scott Rixner, William J. Dally, Ujval J. Kapasi, Peter R. Mattson, John D. Owens
2000MICROEfficient conditional operations for data-parallel architectures.Ujval J. Kapasi, William J. Dally, Scott Rixner, Peter R. Mattson, John D. Owens, Brucek Khailany
1998ICCDThe effects of explicitly parallel mechanisms on the multi-ALU processor cluster pipeline.Andrew Chang, William J. Dally, Stephen W. Keckler, Nicholas P. Carter, Whay Sing Lee
1998ISCAArchitecture of a Message-Driven Processor.William J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, D. Scott Wills
1998ISCARetrospective: the J-machine.William J. Dally, Andrew A. Chien, Stuart Fiske, Waldemar Horwat, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, Ellen Spertus, Deborah A. Wallach, D. Scott Wills, Andrew Chang, John S. Keen
1998ISCAExploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor.Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang, Whay Sing Lee
1998MICROA Bandwidth-efficient Architecture for Media Processing.Scott Rixner, William J. Dally, Ujval J. Kapasi, Brucek Khailany, Abelardo Lpez-Lagunas, Peter R. Mattson, John D. Owens
1995HPCAThread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors.Stuart Fiske, William J. Dally
1995HPCAThe Named-State Register File: Implementation and Performance.Peter R. Nuth, William J. Dally
1995MICROThe M-Machine multicomputer.Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter, Andrew Chang, Yevgeny Gurevich, Whay Sing Lee
1995PPoPPEvaluating the Locality Benefits of Active Messages.Ellen Spertus, William J. Dally
1994ASPLOSHardware Support for Fast Capability-based Addressing.Nicholas P. Carter, Stephen W. Keckler, William J. Dally
1994CIKMXEL: Extended Ephemeral Logging for Log Storage Management.John S. Keen, William J. Dally
1994HOTIArchitecture and implementation of the reliable router.William J. Dally, Larry R. Dennison, David Money Harris, Kinhong Kan, Thucydides Xanthopoulos
1993ISCAThe J-Machine Multicomputer: An Architectural Evaluation.Michael D. Noakes, Deborah A. Wallach, William J. Dally
1993ISCAEvaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5.Ellen Spertus, Seth Copen Goldstein, Klaus E. Schauser, Thorsten von Eicken, David E. Culler, William J. Dally
1993SIGMODPerformance Evaluation of Ephemeral Logging.John S. Keen, William J. Dally
1992ICCDThe Message Driven Processor: An Integrated Multicomputer Processing Element.William J. Dally, Andrew A. Chien, Stuart Fiske, Gregory A. Fyler, Waldemar Horwat, John S. Keen, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, D. Scott Wills
1992ICCDMDP Design Tools and Methods.Richard A. Lethin, William J. Dally
1992ICCDThe J-Machine Network.Peter R. Nuth, William J. Dally
1992ISCAProcessor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism.Stephen W. Keckler, William J. Dally
1991ICCDA Mechanism for Efficient Context Switching.Peter R. Nuth, William J. Dally
1991ICPPExperiences Implementing Dataflow on a General-Purpose Parallel Computer.Ellen Spertus, William J. Dally
1990ICCDSimultaneous bidirectional signalling for IC systems.Kevin Lam, Larry R. Dennison, William J. Dally
1990ISCAVirtual-Channel Flow Control.William J. Dally
1990PPoPPConcurrent Aggregates (CA).Andrew A. Chien, William J. Dally
1989ASPLOSMicro-Optimization of Floating Point Operations.William J. Dally
1989DACAlgorithms for Accuracy Enhancement in a Hardware Logic Simulator.Prathima Agrawal, Raffi Tutundjian, William J. Dally
1989PLDIExperience with CST: Programming and Implementation.Waldemar Horwat, Andrew A. Chien, William J. Dally
1988ISCAThe Reconfigurable Arithmetic Processor.Stuart Fiske, William J. Dally
1987DACArchitecture and Design of the MARS Hardware Accelerator.Prathima Agrawal, William J. Dally, Ahmed K. Ezzat, W. C. Fischer, H. V. Jagadish, A. S. Krishnakumar
1987ISCAArchitecture of a Message-Driven Processor.William J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, D. Scott Wills
1985ISCAAn Object Oriented Architecture.William J. Dally, James T. Kajiya