Xianqing Yao
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
3
Active years
2016–2017
Best venue rank
A
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2017 | FPGA | Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only). | Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei |
| 2017 | ISCAS | Memory fartitioning-based modulo scheduling for high-level synthesis. | Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei |
| 2016 | ICCAD | Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory. | Shouyi Yin, Xianqing Yao, Tianyi Lu, Leibo Liu, Shaojun Wei |