| 2024 | AAAI | Contrastive Balancing Representation Learning for Heterogeneous Dose-Response Curves Estimation. | Minqin Zhu, Anpeng Wu, Haoxuan Li, Ruoxuan Xiong, Bo Li, Xiaoqing Yang, Xuan Qin, Peng Zhen, Jiecheng Guo, Fei Wu, Kun Kuang |
| 2024 | VTC | A Data Synchronization Incentive Scheme in Vehicular Digital Twin Network with Stackelberg Game. | Jingru Tan, Xiaoqing Yang, Jinkai Zheng, Tom H. Luan, Longxiang Gao, Zhou Su |
| 2022 | GLOBECOM | Data Synchronization for Vehicular Digital Twin Network. | Xiaoqing Yang, Jinkai Zheng, Tom H. Luan, Rui Li, Zhou Su, Mianxiong Dong |
| 2021 | IJCNN | Efficient Subgraph Pruning & Embedding for Multi-Relation QA over Knowledge Graph. | Jiamin Lu, Zixuan Zhang, Xiaoqing Yang, Jun Feng |
| 2020 | AAAI | An Attention-Based Graph Neural Network for Heterogeneous Structural Learning. | Huiting Hong, Hantao Guo, Yucheng Lin, Xiaoqing Yang, Zang Li, Jieping Ye |
| 2020 | KDD | HetETA: Heterogeneous Information Network Embedding for Estimating Time of Arrival. | Huiting Hong, Yucheng Lin, Xiaoqing Yang, Zang Li, Kun Fu, Zheng Wang, Xiaohu Qie, Jieping Ye |
| 2020 | KDD | Dynamic Heterogeneous Graph Neural Network for Real-time Event Prediction. | Wenjuan Luo, Han Zhang, Xiaodi Yang, Lin Bo, Xiaoqing Yang, Zang Li, Xiaohu Qie, Jieping Ye |
| 2014 | VLSID | Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire. | Xing Wei, Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yi Diao, Yu-Liang Wu |
| 2012 | DATE | Almost every wire is removable: A modeling and solution for removing any circuit wire. | Xiaoqing Yang, Tak-Kei Lam, Wai-Chung Tang, Yu-Liang Wu |
| 2011 | ASPDAC | On applying erroneous clock gating conditions to further cut down power. | Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yu-Liang Wu |
| 2010 | DAC | ECR: a low complexity generalized error cancellation rewiring scheme. | Xiaoqing Yang, Tak-Kei Lam, Yu-Liang Wu |
| 2010 | ISCAS | Improving redundancy addition and removal using unreachable states for sequential circuits. | Xiaoqing Yang, Zigang Xiao, Yu-Liang Wu |
| 2007 | DAC | EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL Procedure. | Shujun Deng, Jinian Bian, Weimin Wu, Xiaoqing Yang, Yanni Zhao |