Y. Sakataya
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
1986–1986
Best venue rank
A*
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1986 | DAC | Incremental logic synthesis through gate logic structure identification. | T. Shinsha, T. Kubo, Y. Sakataya, J. Koshishita, Koichiro Ishihara |