| 2022 | ASPDAC | Heterogeneous Memory Architecture Accommodating Processing-in-Memory on SoC for AIoT Applications. | Kangyi Qiu, Yaojun Zhang, Bonan Yan, Ru Huang |
| 2018 | DATE | Exploring the opportunity of implementing neuromorphic computing systems with spintronic devices. | Bonan Yan, Fan Chen, Yaojun Zhang, Chang Song, Hai Li, Yiran Chen |
| 2016 | ASPDAC | A novel PUF based on cell error rate distribution of STT-RAM. | Xian Zhang, Guangyu Sun, Yaojun Zhang, Yiran Chen, Hai Li, Wujie Wen, Jia Di |
| 2015 | DATE | Giant spin hall effect (GSHE) logic design for low power application. | Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai Li, Yiran Chen |
| 2014 | ASPDAC | STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures. | Xiaoxiao Liu, Yong Li, Yaojun Zhang, Alex K. Jones, Yiran Chen |
| 2014 | DAC | A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability. | Enes Eken, Yaojun Zhang, Wujie Wen, Rajiv V. Joshi, Hai Li, Yiran Chen |
| 2014 | DAC | Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory. | Mengjie Mao, Wujie Wen, Yaojun Zhang, Yiran Chen, Hai (Helen) Li |
| 2014 | DAC | State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System. | Wujie Wen, Yaojun Zhang, Mengjie Mao, Yiran Chen |
| 2013 | ASPDAC | Loadsa: A yield-driven top-down design method for STT-RAM array. | Wujie Wen, Yaojun Zhang, Lu Zhang, Yiran Chen |
| 2013 | DATE | DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems. | Jie Guo, Wujie Wen, Yaojun Zhang, Sicheng Li, Hai Li, Yiran Chen |
| 2013 | ICCAD | ADAMS: asymmetric differential STT-RAM cell structure for reliable and high-performance applications. | Yaojun Zhang, Ismail Bayram, Yu Wang, Hai Li, Yiran Chen |
| 2013 | ICIG | Pseudo-Three-Dimensional Navigation in Helical Scan Security Inspection. | Bin Li, Baolei Li, Yang Mo, Yaojun Zhang |
| 2013 | ISCAS | MLC STT-RAM design considering probabilistic and asymmetric MTJ switching. | Yaojun Zhang, Lu Zhang, Yiran Chen |
| 2012 | ASPDAC | Probabilistic design in spintronic memory and logic circuit. | Yiran Chen, Yaojun Zhang, Peiyuan Wang |
| 2012 | DAC | PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method. | Wujie Wen, Yaojun Zhang, Yiran Chen, Yu Wang, Yuan Xie |
| 2012 | DATE | Asymmetry of MTJ switching and its implication to STT-RAM designs. | Yaojun Zhang, Xiaobin Wang, Yong Li, Alex K. Jones, Yiran Chen |
| 2012 | ICCAD | Multi-level cell STT-RAM: Is it realistic or just a dream? | Yaojun Zhang, Lu Zhang, Wujie Wen, Guangyu Sun, Yiran Chen |
| 2012 | ISLPED | Improving energy efficiency of write-asymmetric memories by log style write. | Guangyu Sun, Yaojun Zhang, Yu Wang, Yiran Chen |
| 2011 | ICCAD | STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view. | Yaojun Zhang, Xiaobin Wang, Yiran Chen |