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Yasuaki Ito

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

31

Venues

11

Active years

2002–2024

Best venue rank

National

Where they publish

Papers

31 indexed papers, newest first.

YearVenueTitleAuthors
2024PPAMA GPU Implementation of McMurchie-Davidson Algorithm for Two-Electron Repulsion Integral Computation.Haruto Fujii, Yasuaki Ito, Nobuya Yokogawa, Kanta Suzuki, Satoki Tsuji, Koji Nakano, Akihiko Kasagi
2022ICANNBERT-Based Scientific Paper Quality Prediction.Taiki Sasaki, Yasuaki Ito, Koji Nakano, Akihiko Kasagi
2020ICPPHuffman Coding with Gap Arrays for GPU Acceleration.Naoya Yamamoto, Koji Nakano, Yasuaki Ito, Daisuke Takafuji, Akihiko Kasagi, Tsuguchika Tabaru
2020ICPPAdaptive Bulk Search: Solving Quadratic Unconstrained Binary Optimization Problems on Multiple GPUs.Ryota Yasudo, Koji Nakano, Yasuaki Ito, Masaru Tatekawa, Ryota Katsuki, Takashi Yazane, Yoko Inaba
2019PPAMEfficient Triangular Matrix Vector Multiplication on the GPU.Takahiro Inoue, Hiroki Tokura, Koji Nakano, Yasuaki Ito
2019PPAMStained Glass Image Generation Using Voronoi Diagram and Its GPU Acceleration.Hironobu Kobayashi, Yasuaki Ito, Koji Nakano
2019PPAMEfficient cuDNN-Compatible Convolution-Pooling on the GPU.Shunsuke Suita, Takahiro Nishimura, Hiroki Tokura, Koji Nakano, Yasuaki Ito, Akihiko Kasagi, Tsuguchika Tabaru
2017ICPPSimple and Fast Parallel Algorithms for the Voronoi Map and the Euclidean Distance Map, with GPU Implementations.Takumi Honda, Shinnosuke Yamamoto, Hiroaki Honda, Koji Nakano, Yasuaki Ito
2017PPAMAlmost Optimal Column-wise Prefix-sum Computation on the GPU.Hiroki Tokura, Toru Fujita, Koji Nakano, Yasuaki Ito
2017PPAMA GPU Implementation of Bulk Execution of the Dynamic Programming for the Optimal Polygon Triangulation.Kohei Yamashita, Yasuaki Ito, Koji Nakano
2016ICA3PPLight Loss-Less Data Compression, with GPU Implementation.Shunji Funasaka, Koji Nakano, Yasuaki Ito
2016ICA3PPAn Efficient Implementation of LZW Compression in the FPGA.Xin Zhou, Yasuaki Ito, Koji Nakano
2015ISPDCGPU-Accelerated Digital Halftoning by the Local Exhaustive Search.Hiroaki Kouge, Yasuaki Ito, Koji Nakano
2015ISPDCOptimal Parallel Hardware K-Sorter and Top K-Sorter, with FPGA Implementations.Naoyuki Matsumoto, Koji Nakano, Yasuaki Ito
2015PDPOptimality of Fundamental Parallel Algorithms on the Hierarchical Memory Machine, with GPU Implementation.Koji Nakano, Yasuaki Ito
2015PPAMA Parallel Algorithm for LZW Decompression, with GPU Implementation.Shunji Funasaka, Koji Nakano, Yasuaki Ito
2015PPAMParallel FDFM Approach for Computing GCDs Using the FPGA.Xin Zhou, Koji Nakano, Yasuaki Ito
2014ICA3PPGPU-Accelerated Verification of the Collatz Conjecture.Takumi Honda, Yasuaki Ito, Koji Nakano
2014ICA3PPA GPU Implementation of Clipping-Free Halftoning Using the Direct Binary Search.Hiroaki Koge, Yasuaki Ito, Koji Nakano
2014ICA3PPC2CU : A CUDA C Program Generator for Bulk Execution of a Sequential Algorithm.Daisuke Takafuji, Koji Nakano, Yasuaki Ito
2014ICPPParallel Algorithms for the Summed Area Table on the Asynchronous Hierarchical Memory Machine, with GPU implementations.Akihiko Kasagi, Koji Nakano, Yasuaki Ito
2013ICPPAn Optimal Offline Permutation Algorithm on the Hierarchical Memory Machine, with the GPU Implementation.Akihiko Kasagi, Koji Nakano, Yasuaki Ito
2012ICA3PPAccelerating the Dynamic Programming for the Optimal Polygon Triangulation on the GPU.Kazufumi Nishida, Koji Nakano, Yasuaki Ito
2009ISPAA Hardware-Software Cooperative Approach for the Exhaustive Verification of the Collatz Conjecture.Yasuaki Ito, Koji Nakano
2009PDCATAn Efficient Parallel Sorting Compatible with the Standard qsort.Duhu Man, Yasuaki Ito, Koji Nakano
2009PDCATA Simple Parallel Convex Hulls Algorithm for Sorted Points and the Performance Evaluation on the Multicore Processors.Masaya Nakagawa, Duhu Man, Yasuaki Ito, Koji Nakano
2008EUCA Tiny Processing System for Education and Small Embedded Systems on the FPGAs.Koji Nakano, Kensuke Kawakami, Koji Shigemoto, Yuki Kamada, Yasuaki Ito
2008ICPADSProcessor, Assembler, and Compiler Design Education Using an FPGA.Koji Nakano, Yasuaki Ito
2008PDCATOptimized Component Labeling Algorithm for Using in Medium Sized FPGAs.Yasuaki Ito, Koji Nakano
2006ISPARandomized Leader Election Protocols in Noisy Radio Networks with a Single Transceiver.Jacir Luiz Bordim, Yasuaki Ito, Koji Nakano
2002HiPCAccelerating the CKY Parsing Using FPGAs.Jacir Luiz Bordim, Yasuaki Ito, Koji Nakano