Yehea I. Ismail

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

Venues

Active years

1998–2016

Best venue rank

Where they publish

Papers

72 indexed papers, newest first.

Year	Venue	Title	Authors
2016	ISCAS	Five-level hybrid DC-DC converter with enhanced light-load efficiency.	Abdullah Abdulslam, Farid El-Sehrawy, Yehea I. Ismail
2015	ISCAS	A tunable multi-band/multi-standard receiver front-end supporting LTE.	Hoda Abdelsalam, Emad Hegazi, Hassan Mostafa, Yehea I. Ismail
2015	ISCAS	Design of adiabatic TSV, SWCNT TSV, and Air-Gap Coaxial TSV.	Khaled Salah, Yehea I. Ismail
2014	ISCAS	Low-power all-digital manchester-encoding-based high-speed serdes transceiver for on-chip networks.	Abdelrahman H. Elsayed, Ramy N. Tadros, Maged Ghoneima, Yehea I. Ismail
2014	ISCAS	A novel dimensional analysis method for TSV modeling and analysis in three dimensional integrated circuits.	Khaled Salah, Yehea I. Ismail
2014	ISCAS	A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks.	Ramy N. Tadros, Abdelrahman H. Elsayed, Maged Ghoneima, Yehea I. Ismail
2013	ISCAS	TSV-based on-chip inductive coupling communications.	Khaled Salah, Alaa B. El-Rouby, Hani F. Ragai, Yehea I. Ismail
2012	ISCAS	A 16Gbps low power self-timed SerDes transceiver for multi-core communication.	Ezz El-Din O. Hussein, Sally Safwat, Maged Ghoneima, Yehea I. Ismail
2012	ISCAS	A 5-10GHz low power bang-bang all digital PLL based on programmable digital loop filter.	Sally Safwat, Amr Lotfy, Maged Ghoneima, Yehea I. Ismail
2012	ISCAS	A closed form expression for TSV-based on-chip spiral inductor.	Khaled Salah, Alaa B. El-Rouby, Hani F. Ragai, Yehea I. Ismail
2011	ASPDAC	Equivalent lumped element models for various n-port Through Silicon Vias networks.	Khaled Salah, Hani F. Ragai, Yehea I. Ismail, Alaa B. El-Rouby
2011	ISCAS	A Comprehensive Tapered buffer optimization algorithm for unified design metrics.	Song Liu, Seda Ogrenci Memik, Yehea I. Ismail
2011	ISCAS	A dynamic calibration scheme for on-chip process and temperature variations.	Mina Raymond, Maged Ghoneima, Yehea I. Ismail
2011	ISCAS	A 12Gbps all digital low power SerDes transceiver for on-chip networking.	Sally Safwat, Ezz El-Din O. Hussein, Maged Ghoneima, Yehea I. Ismail
2011	ISCAS	Compact lumped element model for TSV in 3D-ICs.	Khaled Salah, Alaa B. El-Rouby, Hani F. Ragai, Karim Amin, Yehea I. Ismail
2011	ISCAS	Fast hysteretic control of on-chip multi-phase switched-capacitor dc-dc converters.	Loai G. Salem, Yehea I. Ismail
2010	ISCAS	A novel variation insensitive clock distribution methodology.	Ezz El-Din O. Hussein, Yehea I. Ismail
2008	ISCAS	Interconnect design and limitations in nanoscale technologies.	Yehea I. Ismail
2008	ISCAS	Power-supply-variation-aware timing analysis of synchronous systems.	Sami Kirolos, Yehia Massoud, Yehea I. Ismail
2008	ISCAS	Accurate analytical delay modeling of CMOS clock buffers considering power supply variations.	Sami Kirolos, Yehia Massoud, Yehea I. Ismail
2007	ICCAD	Multi-layer interconnect performance corners for variation-aware timing analysis.	Frank Huebbers, Ali Dasdan, Yehea I. Ismail
2007	ICCAD	A self-adjusting clock tree architecture to cope with temperature variations.	Jieyi Long, Ja Chun Ku, Seda Ogrenci Memik, Yehea I. Ismail
2007	ICCAD	Including inductance in static timing analysis.	Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail
2007	ISCAS	Approximate Frequency Response Models for RLC Power Grids.	DiaaEldin Khalil, Yehea I. Ismail
2007	ISCAS	Attaining Thermal Integrity in Nanometer Chips.	Ja Chun Ku, Yehea I. Ismail
2007	ISCAS	A Compact and Accurate Temperature-Dependent Model for CMOS Circuit Delay.	Ja Chun Ku, Yehea I. Ismail
2007	ISCAS	Variable Threshold Voltage Design Scheme for CMOS Tapered Buffers.	Ahmed Shebaita, Yehea I. Ismail
2007	ISLPED	Thermal-aware methodology for repeater insertion in low-power VLSI circuits.	Ja Chun Ku, Yehea I. Ismail
2007	ISPASS	Modeling and Characterizing Power Variability in Multicore Architectures.	Ke Meng, Frank Huebbers, Russ Joseph, Yehea I. Ismail
2007	SC	Variable latency caches for nanoscale processor.	Serkan Ozdemir, Arindam Mallik, Ja Chun Ku, Gokhan Memik, Yehea I. Ismail
2006	ASPDAC	Area optimization for leakage reduction and thermal stability in nanometer scale technologies.	Ja Chun Ku, Yehea I. Ismail
2006	DAC	Computation of accurate interconnect process parameter values for performance corners under process variations.	Frank Huebbers, Ali Dasdan, Yehea I. Ismail
2006	ICCAD	Importance of volume discretization of single and coupled interconnects.	Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail
2006	ICCAD	A timing dependent power estimation framework considering coupling.	Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou
2006	ICCD	FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling.	Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack
2006	ISCAS	Reducing the data switching activity of serialized datastreams.	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
2006	ISCAS	Optimum sizing of power grids for IR drop.	DiaaEldin Khalil, Yehea I. Ismail
2006	ISLPED	Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance.	Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De
2005	DAC	Piece-wise approximations of RLCK circuit responses using moment matching.	Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu
2005	DAC	Statistical static timing analysis: how simple can we get?	Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail
2005	DSN	Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files.	Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, Yehea I. Ismail
2005	ICCAD	Serial-link bus: a low-power on-chip bus architecture.	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De
2005	ICCAD	Expanding the frequency range of AWE via time shifting.	Ahmed M. Shebaita, Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
2005	ICCD	A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors.	Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail
2005	ISCAS	Accurate decoupling of capacitively coupled buses.	Maged Ghoneima, Yehea I. Ismail
2005	ISCAS	Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses.	Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Vivek De
2005	MICRO	Thermal Management of On-Chip Caches Through Power Density Minimization.	Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail
2004	ICCAD	Modeling unbuffered latches for timing analysis.	Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
2004	ICCAD	Formal derivation of optimal active shielding for low-power on-chip buses.	Maged Ghoneima, Yehea I. Ismail
2004	ICCAD	Computation of signal threshold crossing times directly from higher order moments.	Yehea I. Ismail, Chirayu S. Amin
2004	ISCAS	Powder-based fabrication techniques for single-wall carbon nanotube circuits.	Daniel Dai, Yehea I. Ismail, Wei Wang, Hanif M. Ladak
2004	ISCAS	Low power coupling-based encoding for on-chip buses.	Maged Ghoneima, Yehea I. Ismail
2004	ISCAS	Effect of relative delay on the dissipated energy in coupled interconnects.	Maged Ghoneima, Yehea I. Ismail
2004	ISLPED	Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses.	Maged Ghoneima, Yehea I. Ismail
2003	DAC	Realizable RLCK circuit crunching.	Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail
2003	DAC	Optimum positioning of interleaved repeaters In bidirectional buses.	Maged Ghoneima, Yehea I. Ismail
2003	DAC	Efficient model order reduction including skin effect.	Shizhong Mei, Chirayu S. Amin, Yehea I. Ismail
2003	ICCAD	Weibull Based Analytical Waveform Model.	Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
2003	ISCAS	Realizable reduction of RLC circuits using node elimination.	Masud H. Chowdhury, Chirayu S. Amin, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter
2003	ISCAS	Accurate rise time and overshoots estimation in RLC interconnects.	Noha H. Mahmoud, Yehea I. Ismail
2003	ISCAS	Modeling skin effect with reduced decoupled R-L circuits.	Shizhong Mei, Yehea I. Ismail
2002	ICCAD	Efficient model order reduction via multi-node moment matching.	Yehea I. Ismail
2002	ISCAS	Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance.	Masud H. Chowdhury, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter
2002	ISCAS	Evaluating noise pulses in RC networks due to capacitive coupling.	Yehea I. Ismail
2000	ISCAS	Sensitivity of interconnect delay to on-chip inductance.	Yehea I. Ismail, Eby G. Friedman
1999	DAC	Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits.	Yehea I. Ismail, Eby G. Friedman
1999	DAC	Equivalent Elmore Delay for	Yehea I. Ismail, Eby G. Friedman, Jos Luis Neves
1999	ICCAD	Repeater insertion in tree structured inductive interconnect.	Yehea I. Ismail, Eby G. Friedman, Jos Luis Neves
1999	ISCAS	Repeater insertion in RLC lines for minimum propagation delay.	Yehea I. Ismail, Eby G. Friedman
1999	ISCAS	Signal waveform characterization in RLC trees.	Yehea I. Ismail, Eby G. Friedman, Jos Luis Neves
1998	DAC	Figures of Merit to Characterize the Importance of On-Chip Inductance.	Yehea I. Ismail, Eby G. Friedman, Jos Luis Neves
1998	ISLPED	Power dissipated by CMOS gates driving lossless transmission lines.	Yehea I. Ismail, Eby G. Friedman, Jos Luis Neves