| 2026 | ASPDAC | C3PO: Commercial-Quality Global Placement via Coherent, Concurrent Timing, Routability, and Wirelength Optimization. | Yi-Chen Lu, Hao-Hsiang Hsiao, Rongjian Liang, Wen-Hao Liu, Haoxing Ren |
| 2026 | ASPDAC | Differentiable Tier Assignment for Timing and Congestion-Aware Routing in 3D ICs. | Yuan-Hsiang Lu, Hao-Hsiang Hsiao, Yi-Chen Lu, Haoxing Ren, Sung Kyu Lim |
| 2025 | DAC | DCO-3D: Differentiable Congestion Optimization in 3D ICs. | Hao-Hsiang Hsiao, Yi-Chen Lu, Pruek Vanna-Iampikul, Anthony Agnesina, Rongjian Liang, Yuan-Hsiang Lu, Haoxing Ren, Sung Kyu Lim |
| 2025 | DAC | INSTA: An Ultra-Fast, Differentiable, Statistical Static Timing Analysis Engine for Industrial Physical Design Applications. | Yi-Chen Lu, Zhizheng Guo, Kishor Kunal, Rongjian Liang, Haoxing Ren |
| 2025 | ICCAD | BUFFALO: PPA-Configurable, LLM-based Buffer Tree Generation via Group Relative Policy Optimization. | Hao-Hsiang Hsiao, Yi-Chen Lu, Sung Kyu Lim, Haoxing Ren |
| 2025 | ICCAD | Invited Paper: LLM-Enhanced GPU-Optimized Physical Design at Scale. | Yi-Chen Lu, Hao-Hsiang Hsiao, Haoxing Ren |
| 2025 | ICCAD | Invited Paper: 2025 ICCAD CAD Contest Problem C: Incremental Placement Optimization Beyond Detailed Placement: Simultaneous Gate Sizing, Buffering, and Cell Relocation. | Yi-Chen Lu, Rongjian Liang, Wen-Hao Liu, Haoxing Ren |
| 2024 | DAC | ML-based Physical Design Parameter Optimization for 3D ICs: From Parameter Selection to Optimization. | Hao-Hsiang Hsiao, Pruek Vanna-Iampikul, Yi-Chen Lu, Sung Kyu Lim |
| 2023 | DAC | RL-CCD: Concurrent Clock and Data Optimization using Attention-Based Self-Supervised Reinforcement Learning. | Yi-Chen Lu, Wei-Ting Chan, Deyuan Guo, Sudipto Kundu, Vishal Khandelwal, Sung Kyu Lim |
| 2022 | ICCAD | On Advancing Physical Design Using Graph Neural Networks. | Yi-Chen Lu, Sung Kyu Lim |
| 2022 | ISLPED | 3D IC Tier Partitioning of Memory Macros: PPA vs. Thermal Tradeoffs. | Lingjun Zhu, Nesara Eranna Bethur, Yi-Chen Lu, Youngsang Cho, Yunhyeok Im, Sung Kyu Lim |
| 2021 | DAC | RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning. | Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim |
| 2021 | ICCAD | Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning. | Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim |
| 2020 | DAC | TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs. | Yi-Chen Lu, Sai Surya Kiran Pentapati, Lingjun Zhu, Kambiz Samadi, Sung Kyu Lim |
| 2020 | ICCAD | A Fast Learning-Driven Signoff Power Optimization Framework. | Yi-Chen Lu, Siddhartha Nath, Sai Surya Kiran Pentapati, Sung Kyu Lim |
| 2019 | ICCAD | GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization. | Yi-Chen Lu, Jeehyun Lee, Anthony Agnesina, Kambiz Samadi, Sung Kyu Lim |
| 2016 | WCNC | An energy-efficient multicast protocol for ZigBee-based networks. | Shu-Chiung Hu, Chia-Hung Tsai, Yi-Chen Lu, Meng-Shiuan Pan, Yu-Chee Tseng |
| 2015 | IJCNN | Single channel wireless EEG device for real-time fatigue level detection. | Li-Wei Ko, Wei-Kai Lai, Wei-Gang Liang, Chun-Hsiang Chuang, Shao-Wei Lu, Yi-Chen Lu, Tien-Yang Hsiung, Hsu-Hsuan Wu, Chin-Teng Lin |