Yi-Jong Yeh
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
3
Active years
2001–2005
Best venue rank
C
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | FORTE | Automatic Partitioner for Behavior Level Distributed Logic Simulation. | Kai-Hui Chang, Jeh-Yen Kang, Han-Wei Wang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo |
| 2004 | ATVA | A Temporal Assertion Extension to Verilog. | Kai-Hui Chang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo |
| 2001 | ISCAS | An optimization-based low-power voltage scaling technique using multiple supply voltages. | Yi-Jong Yeh, Sy-Yen Kuo |