Yi-Wei Chiu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
2
Active years
2008–2016
Best venue rank
C
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2016 | ISCAS | A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper. | Yi-Wei Chiu, Yu-Hao Hu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang |
| 2015 | ISCAS | A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive. | Chi-Hao Hong, Yi-Wei Chiu, Jun-Kai Zhao, Shyh-Jye Jou, Wen-Tai Wang, Reed Lee |
| 2013 | ISLPED | A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist. | Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang |
| 2011 | ISLPED | 8T single-ended sub-threshold SRAM with cross-point data-aware write operation. | Yi-Wei Chiu, Jihi-Yu Lin, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang |
| 2008 | ISCAS | A reconfigurable MAC architecture implemented with mixed-Vt standard cell library. | Li-Rong Wang, Yi-Wei Chiu, Chia-Lin Hu, Ming-Hsien Tu, Shyh-Jye Jou, Chung-Len Lee |