Yijin Guan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
10
Venues
8
Active years
2015–2026
Best venue rank
A*
Where they publish
Papers
10 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ISCA | Tetris: Efficient Long-context LLM Serving with Chunkwise Dynamic Sequence Parallelism. | Cong Li, Yuzhe Yang, Xuegui Zheng, Qifan Yang, Yijin Guan, Size Zheng, Li-Wen Chang, Shufan Liu, Xin Liu, Guangyu Sun |
| 2025 | ASPLOS | CTXNL: A Software-Hardware Co-designed Solution for Efficient CXL-Based Transaction Processing. | Zhao Wang, Yiqi Chen, Cong Li, Yijin Guan, Dimin Niu, Tianchan Guan, Zhaoyang Du, Xingda Wei, Guangyu Sun |
| 2024 | ASPLOS | Salus: A Practical Trusted Execution Environment for CPU-FPGA Heterogeneous Cloud Platforms. | Yu Zou, Yiran Li, Sheng Wang, Le Su, Zhen Gu, Yanheng Lu, Yijin Guan, Dimin Niu, Mingyu Gao, Yuan Xie, Feifei Li |
| 2024 | USENIX | HydraRPC: RPC in the CXL Era. | Teng Ma, Zheng Liu, Chengkun Wei, Jialiang Huang, Youwei Zhuo, Haoyu Li, Ning Zhang, Yijin Guan, Dimin Niu, Mingxing Zhang, Tao Ma |
| 2022 | ICPADS | Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. | Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie |
| 2022 | ISCA | Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network. | Shuangchen Li, Dimin Niu, Yuhao Wang, Wei Han, Zhe Zhang, Tianchan Guan, Yijin Guan, Heng Liu, Linyong Huang, Zhaoyang Du, Fei Xue, Yuanwei Fang, Hongzhong Zheng, Yuan Xie |
| 2021 | DAC | BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices. | Zhe Zhou, Bizhao Shi, Zhe Zhang, Yijin Guan, Guangyu Sun, Guojie Luo |
| 2017 | ASPDAC | FPGA-based accelerator for long short-term memory recurrent neural networks. | Yijin Guan, Zhihang Yuan, Guangyu Sun, Jason Cong |
| 2017 | FCCM | FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates. | Yijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun, Wei Zhang, Jason Cong |
| 2015 | FPGA | Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks. | Chen Zhang, Peng Li, Guangyu Sun, Yijin Guan, Bingjun Xiao, Jason Cong |