Yogesh Dilip Save
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
2012–2013
Best venue rank
National
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2013 | VLSID | Memory Efficient Implementation of Two Graph Based Circuit Simulator for PDE-Electrical Analogy. | Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar |
| 2012 | VLSID | Two Graph Based Circuit Simulator for PDE-Electrical Analogy. | Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar |