Yong-Cheol Bae
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2004–2004
Best venue rank
C
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2004 | ISCAS | A mixed PLL/DLL architecture for low jitter clock generation. | Yong-Cheol Bae, Gu-Yeon Wei |