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Yong Cheol Peter Cho

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

5

Venues

5

Active years

2011–2021

Best venue rank

C

Where they publish

Papers

5 indexed papers, newest first.

YearVenueTitleAuthors
2021ISCASLive Demonstration: A Neural Processor for AI Acceleration.Hyeji Kim, Jaehoon Chung, Kyoung-Seon Shin, Chun-Gi Lyuh, Hyun-Mi Kim, Chan Kim, Yong Cheol Peter Cho, Jeongmin Yang, Je-Seok Ham, Minseok Choi, Jinho Han, Youngsu Kwon
2014ICCDRefresh Enabled Video Analytics (REVA): Implications on power and performance of DRAM supported embedded visual systems.Siddharth Advani, Nandhini Chandramoorthy, Karthik Swaminathan, Kevin M. Irick, Yong Cheol Peter Cho, Jack Sampson, Vijaykrishnan Narayanan
2012ASPDACA reconfigurable platform for the design and verification of domain-specific accelerators.Sungho Park, Yong Cheol Peter Cho, Kevin M. Irick, Vijaykrishnan Narayanan
2011FCCMAn FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization.Sungmin Bae, Yong Cheol Peter Cho, Sungho Park, Kevin M. Irick, Yongseok Jin, Vijaykrishnan Narayanan
2011FPLExploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA.Yong Cheol Peter Cho, Sungmin Bae, Yongseok Jin, Kevin M. Irick, Vijaykrishnan Narayanan