| 2026 | ISCAS | A Layer-Aware Heterogeneous SNN Accelerator Architecture for Energy-Efficient Inference on Resource-Limited FPGAs. | Zeyuan Song, Xingan Sha, Youhua Shi |
| 2019 | ISCAS | Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs. | Jinghao Ye, Nozomu Togawa, Masao Yanagisawa, Youhua Shi |
| 2018 | TrustCom | Hardware Trojan Detection Utilizing Machine Learning Approaches. | Kento Hasegawa, Youhua Shi, Nozomu Togawa |
| 2015 | DATE | A score-based classification method for identifying hardware-trojans at gate-level netlists. | Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa |
| 2013 | ISCAS | Concurrent faulty clock detection for crypto circuits against clock glitch based DFA. | Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa |
| 2013 | PRDC | Secure Scan Design with Dynamically Configurable Connection. | Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa |
| 2010 | ISCAS | State-dependent changeable scan architecture against scan-based side channel attacks. | Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2009 | ITC | Design-for-secure-test for crypto cores. | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2008 | ASPDAC | GECOM: Test data compression combined with all unknown response masking. | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2008 | ASPDAC | Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2 | Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2007 | ISCAS | Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2006 | ASPDAC | FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. | Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2003 | ASPDAC | Multiple test set generation method for LFSR-based BIST. | Youhua Shi, Zhe Zhang |