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Youn-Long Lin

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

37

Venues

11

Active years

1987–2023

Best venue rank

A*

Where they publish

Papers

37 indexed papers, newest first.

YearVenueTitleAuthors
2023CVPRNeighborTrack: Single Object Tracking by Bipartite Matching with Neighbor Tracklets and Its Applications to Sports.Yu-Hsi Chen, Chien-Yao Wang, Cheng-Yun Yang, Hung-Shuo Chang, Youn-Long Lin, Yung-Yu Chuang, Hong-Yuan Mark Liao
2022BMVCSearchTrack: Multiple Object Tracking with Object-Customized Search and Motion-Aware Features.Zhong-Min Tsai, Yu-Ju Tsai, Chien-Yao Wang, Hong-Yuan Mark Liao, Youn-Long Lin, Yung-Yu Chuang
2022MICCAIHarDNet-DFUS: Enhancing Backbone and Decoder of HarDNet-MSEG for Diabetic Foot Ulcer Image Segmentation.Ting-Yu Liao, Ching-Hui Yang, Yu-Wen Lo, Kuan-Ying Lai, Po-Huai Shen, Youn-Long Lin
2019ICCVHarDNet: A Low Memory Traffic Network.Ping Chao, Chao-Yang Kao, Yu-Shan Ruan, Chien-Hsiang Huang, Youn-Long Lin
2009ISCASA High throughput CABAC Encoder for Ultra High Resolution Video.Li-Cian Wu, Youn-Long Lin
2008ISCASA motion compensation system with a high efficiency reference frame pre-fetch scheme for QFHD H.264/AVC decoding.Ping Chao, Youn-Long Lin
2007ICASSPA High-Performance Hardwired CABAC Decoder.Jian-Wen Chen, Youn-Long Lin
2006ASPDACIntroduction to H.264 advanced video coding.Jian-Wen Chen, Chao-Yang Kao, Youn-Long Lin
2006ASPDACA near optimal deblocking filter for H.264 advanced video coding.Shen-Yu Shih, Cheng-Ru Chang, Youn-Long Lin
2005DATEIntegration, Verification and Layout of a Complex Multimedia SOC.Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin
2005ISCASA hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC.Jian-Wen Chen, Cheng-Ru Chang, Youn-Long Lin
2005ISCASAn AMBA-compliant deblocking filter IP for H.264/AVC.Sheng-Yu Shih, Cheng-Ru Chang, Youn-Long Lin
2001ASPDACA 3-step approach for performance-driven whole-chip routing.Yih-Chih Chou, Youn-Long Lin
2000ASPDACArray allocation taking into account SDRAM characteristics.Hong-Kai Chang, Youn-Long Lin
2000ASPDACA VLSI implementation of the blowfish encryption/decryption algorithm.Michael C.-J. Lin, Youn-Long Lin
2000ASPDACPerformance-optimal clustering with retiming for sequential circuits.Tzu-Chieh Tien, Youn-Long Lin
1999ASPDACLayout-based Logic Decomposition for Timing Optimization.Yun-Yin Lian, Youn-Long Lin
1999DACA Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning.Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
1998ICCADA graph-partitioning-based approach for multi-layer constrained via minimization.Yih-Chih Chou, Youn-Long Lin
1998ICCADIntegrating logic retiming and register placement.Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, Youn-Long Lin
1997ASPDACComputing brokerage and its application in VLSI design.Youn-Long Lin
1995DACA Transformation-Based Approach for Storage Optimization.Wei-Kai Cheng, Youn-Long Lin
1995DACRegister Minimization beyond Sharing among Variables.Tsung-Yi Wu, Youn-Long Lin
1994ICCDState Assignment for Power and Area Minimization.Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
1993ICCADCombining technology mapping and placement for delay-optimization in FPGA designs.Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
1992ICCADAn effective methodology for functional pipelining.Tsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin
1991DACScheduling for Functional Pipelining and Loop Winding.Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
1991DACAn Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation.Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
1991DACChannel Density Reduction by Routing Over The Cells.Min-Siang Lin, Hourng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin
1990DACLiB: A Cell Layout Generator.Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu
1990DACData Path Allocation Based on Bipartite Weighted Matching.Chu-Yi Huang, Yen-Shen Chen, Youn-Long Lin, Yu-Chin Hsu
1990DACOptimum and Heuristic Data Path Scheduling Under Resource Constraints.Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
1989ICCADAn optimal transistor-chaining algorithm for CMOS cell layout.Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
1989ICCADA new integer linear programming formulation for the scheduling problem in data path synthesis.Jiahn-Humg Lee, Yu-Chin Hsu, Youn-Long Lin
1989ICCADRouting using a pyramid data structure.Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
1988ICCADA detailed router based on simulated evolution.Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
1987DACLES: A Layout Expert System.Youn-Long Lin, Daniel Gajski