| 2026 | ASPLOS | Finding Reusable Instructions via E-Graph Anti-Unification. | Youwei Xiao, Chenyun Yin, Yitian Sun, Yuyang Zou, Yun Liang |
| 2025 | DAC | Cayman: Custom Accelerator Generation with Control Flow and Data Access Optimization. | Youwei Xiao, Fan Cui, Zizhang Luo, Weijie Peng, Yun Liang |
| 2025 | FPGA | An Empirical Comparision of LLM-based Hardware Design and High-level Synthesis. | Fan Cui, Youwei Xiao, Kexing Zhou, Yun Liang |
| 2025 | ICCAD | Clay: High-level ASIP Framework for Flexible Microarchitecture-Aware Instruction Customization. | Weijie Peng, Youwei Xiao, Yuyang Zou, Zizhang Luo, Yun (Eric) Liang |
| 2025 | ICCAD | Invited Paper: APS: Open-Source Hardware-Software Co-Design Framework for Agile Processor Specialization. | Youwei Xiao, Yuyang Zou, Yansong Xu, Yuhao Luo, Yitian Sun, Chenyun Yin, Ruifan Xu, Renze Chen, Yun Liang |
| 2024 | FPGA | Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis. | Youwei Xiao, Zizhang Luo, Kexing Zhou, Yun Liang |
| 2024 | ICCAD | OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection. | Fan Cui, Chenyang Yin, Kexing Zhou, Youwei Xiao, Guangyu Sun, Qiang Xu, Qipeng Guo, Yun Liang, Xingcheng Zhang, Demin Song, Dahua Lin |
| 2022 | ICCAD | HECTOR: A Multi-Level Intermediate Representation for Hardware Synthesis Methodologies. | Ruifan Xu, Youwei Xiao, Jin Luo, Yun Liang |