| 2014 | DATE | Leakage-power-aware clock period minimization. | Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh |
| 2013 | ICCAD | Low-power timing closure methodology for ultra-low voltage designs. | Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou |
| 2007 | DAC | Clock Period Minimization with Minimum Delay Insertion. | Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh |
| 2006 | ASPDAC | Fast multi-domain clock skew scheduling for peak current reduction. | Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh |
| 2006 | DAC | Register binding for clock period minimization. | Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu |
| 2006 | ICCAD | State re-encoding for peak current minimization. | Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh |
| 2005 | DAC | Race-condition-aware clock skew scheduling. | Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu |
| 2005 | DAC | Minimizing peak current via opposite-phase clock tree. | Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu |
| 2003 | ICCAD | Clock Period Minimization of Non-Zero Clock Skew Circuits. | Shih-Hsu Huang, Yow-Tyng Nieh |