Yu-Yee Liow
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
1999–2002
Best venue rank
C
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2002 | ISCAS | The design of high-speed pipelined analog-to-digital converters using voltage-mode sampling and current mode processing techniques. | Yu-Yee Liow, Chung-Yu Wu |
| 1999 | ISCAS | A new dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS DRAMs. | Chung-Yu Wu, Yu-Yee Liow |