Yuan-Chen Ho
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2019–2019
Best venue rank
C
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | DDECS | Implementation of FPGA-based Accelerator for Deep Neural Networks. | Tsung-Han Tsai, Yuan-Chen Ho, Ming-Hwa Sheu |