Yuanlin Lu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
2007–2008
Best venue rank
National
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2008 | VLSID | Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation. | Yuanlin Lu, Vishwani D. Agrawal |
| 2007 | VLSID | Statistical Leakage and Timing Optimization for Submicron Process Variation. | Yuanlin Lu, Vishwani D. Agrawal |