| 2016 | FPL | A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. | Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto |
| 2015 | ASPDAC | Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. | Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera |
| 2012 | FPL | A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture. | Toshihiro Kameda, Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye |
| 2011 | FPL | Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures. | Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye |
| 2010 | ASPDAC | Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. | Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
| 2010 | WISA | A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling. | Takehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
| 2009 | ASPDAC | Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. | Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
| 2009 | FPL | Coarse-grained dynamically reconfigurable architecture with flexible reliability. | Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye |
| 2009 | ISLPED | Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits. | Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
| 2008 | ISLPED | Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. | Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
| 2001 | ASPDAC | A dynamically reconfigurable hardware-based cipher chip. | Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa |
| 2001 | ISCAS | VLSI architecture of dynamically reconfigurable hardware-based cipher. | Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa |