| 2025 | DAC | P-DAC: Power-Efficient Photonic Accelerators for LLM Inference. | Wen-Tse Chang, Chun-Feng Wu, Yun-Chen Lo |
| 2023 | DAC | Bit-Serial Cache: Exploiting Input Bit Vector Repetition to Accelerate Bit-Serial Inference. | Yun-Chen Lo, Ren-Shuo Liu |
| 2023 | DAC | Morphable CIM: Improving Operation Intensity and Depthwise Capability for SRAM-CIM Architecture. | Yun-Chen Lo, Ren-Shuo Liu |
| 2023 | ICCD | BICEP: Exploiting Bitline Inversion for Efficient Operation-Unit-Based Compute-in-Memory Architecture: No Retraining Needed! | Yun-Chen Lo, Chia-Chun Wang, Ren-Shuo Liu |
| 2023 | ICCD | Exploiting and Enhancing Computation Latency Variability for High-Performance Time-Domain Computing-in-Memory Neural Network Accelerators. | Chia-Chun Wang, Yun-Chen Lo, Jun-Shen Wu, Yu-Chih Tsai, Chia-Cheng Chang, Tsen-Wei Hsu, Min-Wei Chu, Chuan-Yao Lai, Ren-Shuo Liu |
| 2023 | ICLR | Block and Subword-Scaling Floating-Point (BSFP) : An Efficient Non-Uniform Quantization For Low Precision Inference. | Yun-Chen Lo, Tse-Kuang Lee, Ren-Shuo Liu |
| 2023 | MICRO | Bucket Getter: A Bucket-based Processing Engine for Low-bit Block Floating Point (BFP) DNNs. | Yun-Chen Lo, Ren-Shuo Liu |
| 2022 | ICCAD | ISSA: Input-Skippable, Set-Associative Computing-in-Memory (SA-CIM) Architecture for Neural Network Accelerators. | Yun-Chen Lo, Chih-Chen Yeh, Jun-Shen Wu, Chia-Chun Wang, Yu-Chih Tsai, Wen-Chien Ting, Ren-Shuo Liu |
| 2021 | ASPDAC | Interference-Free Design Methodology for Paper-Based Digital Microfluidic Biochips. | Yun-Chen Lo, Bing Li, Sooyong Park, Kwanwoo Shin, Tsung-Yi Ho |