Zbysek Gajda
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
2006–2010
Best venue rank
A
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2010 | GECCO | When does Cartesian genetic programming minimize the phenotype size implicitly? | Zbysek Gajda, Luks Sekanina |
| 2009 | CEC | Gate-level optimization of polymorphic circuits using Cartesian Genetic Programming. | Zbysek Gajda, Luks Sekanina |
| 2007 | GECCO | Reducing the number of transistors in digital circuits using gate-level evolutionary design. | Zbysek Gajda, Luks Sekanina |
| 2006 | CEC | Extrinsic and Intrinsic Evolution of Multifunctional Combinational Modules. | Luks Sekanina, Toms Martnek, Zbysek Gajda |
| 2006 | DDECS | A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming. | Zbysek Gajda |