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Zeshan Chishti

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

20

Venues

7

Active years

2003–2023

Best venue rank

A*

Where they publish

Papers

20 indexed papers, newest first.

YearVenueTitleAuthors
2023SIGMETRICSArchitectural Support for Efficient Data Movement in Fully Disaggregated Systems.Christina Giannoula, Kailong Huang, Jonathan Tang, Nectarios Koziris, Georgios I. Goumas, Zeshan Chishti, Nandita Vijaykumar
2021MICROImproving Streaming Graph Processing Performance using Input Knowledge.Abanti Basak, Zheng Qu, Jilan Lin, Alaa R. Alameldeen, Zeshan Chishti, Yufei Ding, Yuan Xie
2020ISPASSSAGA-Bench: Software and Hardware Characterization of Streaming Graph Analytics Workloads.Abanti Basak, Jilan Lin, Ryan Lorica, Xinfeng Xie, Zeshan Chishti, Alaa R. Alameldeen, Yuan Xie
2016MICROPath confidence based lookahead prefetching.Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A. L. Narasimha Reddy, Chris Wilkerson, Zeshan Chishti
2015ISCAFlexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions.Ishwar Bhati, Zeshan Chishti, Shih-Lien Lu, Bruce L. Jacob
2015MICROEfficiently prefetching complex address patterns.Manjunath Shevgoor, Sahil Koladiya, Rajeev Balasubramonian, Chris Wilkerson, Seth H. Pugsley, Zeshan Chishti
2014HPCAImproving DRAM performance by parallelizing refreshes with accesses.Kevin Kai-Wei Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu
2014HPCASandbox Prefetching: Safe run-time evaluation of aggressive prefetchers.Seth H. Pugsley, Zeshan Chishti, Chris Wilkerson, Peng-fei Chuang, Robert L. Scott, Aamer Jaleel, Shih-Lien Lu, Kingsum Chow, Rajeev Balasubramonian
2014MICROTransparent Hardware Management of Stacked DRAM as Part of Memory.Jaewoong Sim, Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, Hyesoon Kim
2013DSNOperating SECDED-based caches at ultra-low voltage with FLAIR.Moinuddin K. Qureshi, Zeshan Chishti
2013ISLPEDCoordinated refresh: Energy efficient techniques for DRAM refresh scheduling.Ishwar Bhati, Zeshan Chishti, Bruce L. Jacob
2011ISCAEnergy-efficient cache design using variable-strength error-correcting codes.Alaa R. Alameldeen, Ilya Wagner, Zeshan Chishti, Wei Wu, Chris Wilkerson, Shih-Lien Lu
2010ISCAReducing cache power with low-cost, multi-bit error-correcting codes.Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, Shih-Lien Lu
2010ISLPEDRank-aware cache replacement and write buffering to improve DRAM energy efficiency.Ahmed M. Amin, Zeshan Chishti
2009MICROImproving cache lifetime reliability at ultra-low voltages.Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Shih-Lien Lu
2008ISCATrading off Cache Capacity for Reliability to Enable Low Voltage Operation.Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu
2008MICROShapeshifter: Dynamically changing pipeline width and speed to address process variations.Eric Chun, Zeshan Chishti, T. N. Vijaykumar
2005ISCAOptimizing Replication, Communication, and Capacity Allocation in CMPs.Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar
2004ISCAWire Delay is Not a Problem for SMT (In the Near Future).T. N. Vijaykumar, Zeshan Chishti
2003MICRODistance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures.Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar