Zhijun Huang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
5
Active years
1999–2003
Best venue rank
C
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2003 | ARITH | High-Performance Left-to-Right Array Multiplier Design. | Zhijun Huang, Milos D. Ercegovac |
| 2002 | ISCAS | Two-dimensional signal gating for low-power array multiplier design. | Zhijun Huang, Milos D. Ercegovac |
| 2001 | FCCM | FPGA Implementation of Pipelined On-Line Scheme for 3-D Vector Normalization. | Zhijun Huang, Milos D. Ercegovac |
| 2001 | FPGA | Performance-driven mapping for CPLD architectures. | Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang |
| 1999 | ASPDAC | An Analytical Delay Model for SRAM-Based FPGA Interconnections. | Feng Zhou, Zhijun Huang, Jiarong Tong, Pushan Tang |