| 1998 | Automatic Verification of Mixed-Level Logic Circuits. | F. Keith Hanna |
| 1998 | Symbolic Simulation of the JEM1 Microprocessor. | David A. Greve |
| 1998 | Bisimulation Minimization in an Automata-Theoretic Verification Framework. | Kathi Fisler, Moshe Y. Vardi |
| 1998 | The Formal Design of 1M-gate ASICs. | sgeir Th. Eirksson |
| 1998 | Model Checking VHDL with CV. | David Dharbe, Subash Shankar, Edmund M. Clarke |
| 1998 | An Instruction Set Process Calculus. | Shiu-Kai Chin, Jang Dae Kim |
| 1998 | Alexandria: A Tool for Hierarchical Verification. | Annette Bunker, Trent N. Larson, Michael D. Jones, Phillip J. Windley |
| 1998 | Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification. | Sergey Berezin, Armin Biere, Edmund M. Clarke, Yunshan Zhu |
| 1996 | Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs. | Zijian Zhou, Xiaoyu Song, Sofine Tahar, Eduard Cerny, Francisco Corella, Michel Langevin |
| 1996 | BDDs vs. Zero-Suppressed BDDs: for CTL Symbolic Model Checking of Petri Nets. | Tomohiro Yoneda, Hideyuki Hatori, Atsushi Takahara, Shin-ichi Minato |
| 1996 | Mechanically Checking a Lemma Used in an Automatic Verification Tool. | Phillip J. Windley, Jerry R. Burch |
| 1996 | Automatic Generation of Invariants in Processor Verification. | Jeffrey X. Su, David L. Dill, Clark W. Barrett |
| 1996 | PVS: Combining Specification, Proof Checking, and Model Checking. | Natarajan Shankar |
| 1996 | A Brief Study of BDD Package Performance. | Ellen Sentovich |
| 1996 | A Unified Approach for Combining Different Formalisms for Hardware Verification. | Klaus Schneider, Thomas Kropf |
| 1996 | Hierarchical Verification of Two-Dimensional High-Speed Multiplication in PVS: A Case Study. | Harald Rue |
| 1996 | Modular Verification of Multipliers. | Kavita Ravi, Abelardo Pardo, Gary D. Hachtel, Fabio Somenzi |
| 1996 | Specification of Control Flow Properties for Verification of Synthesized VHDL Designs. | Naren Narasimhan, Ranga Vemuri |
| 1996 | Verification of IEEE Compliant Subtractive Division Algorithms. | Paul S. Miner, James F. Leathrum |
| 1996 | Local Encoding Transformations for Optimizing OBDD-Representations of Finite State Machines. | Christoph Meinel, Thorsten Theobald |
| 1996 | A Methodology for Processor Implementation Verification. | Daniel Lewin, Dean H. Lorenz, Shmuel Ur |
| 1996 | Formal Synthesis in Circuit Design - A Classification and Survey. | Ramayya Kumar, Christian Blumenrhr, Dirk Eisenbiegler, Detlef Schmid |
| 1996 | The Need for Formal Methods for Integrated Circuit Design. | Kurt Keutzer |
| 1996 | Self-Consistency Checking. | Robert B. Jones, Carl-Johan H. Seger, David L. Dill |
| 1996 | Decomposition Techniques for Efficient ROBDD Construction. | Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita |