| 2001 | A Family of Resource-Bound Real-Time Process Algebras. | Insup Lee, Jin-Young Choi, Hee-Hwan Kwak, Anna Philippou, Oleg Sokolsky |
| 2001 | Formal Verification of Peephole Optimizations in Asynchronous Circuits. | Xiaohua Kong, Radu Negulescu |
| 2001 | Stepwise Design with Message Sequence Charts. | Ferhat Khendek, Stephan Bourduas, Daniel Vincent |
| 2001 | Formal Synthesis and Control of Soft Embedded Real-Time Systems. | Pao-Ann Hsiung |
| 2001 | SVL: A Scripting Language for Compositional Verification. | Hubert Garavel, Frdric Lang |
| 2001 | Diagnosing Multiple Faults in Communicating Finite State Machines. | Khaled El-Fakih, Nina Yevtushenko, Gregor von Bochmann |
| 2001 | Distributed Test using Logical Clock. | Jin-Young Choi, Hee Yong Youn, Soonuk Seol, Chuck Yoo |
| 2001 | A PKI-Based End-to-End Secure Infrastructure for Mobile E-Commerce. | Tin-Wo Cheung, Samuel T. Chanson |
| 2001 | Executable Test Sequence for the Protocol Data Flow Property. | Wen-Huei Chen |
| 2001 | A Symbolic Semantics and Bisimulation for Full LOTOS. | Muffy Calder, Carron Shankland |
| 2001 | Implementing a Modal Logic over Data and Processes using XTL. | Jeremy W. Bryans, Carron Shankland |
| 2001 | A Tool for Generating Specifications from a Family of Formal Requirements. | Jan Bredereke |
| 2001 | Time and Action Lock Freedom Properties for Timed Automata. | Howard Bowman |
| 2001 | On Formal Techniques in Protocol Engineering - Example Challenges. | Dines Bjrner |
| 2000 | Implementing CCS in Maude. | Alberto Verdejo, Narciso Mart-Oliet |
| 2000 | Satisfaction up to Liveness. | Ulrich Ultes-Nitsche |
| 2000 | Simulating Multicast Transport Protocols in Estelle. | Justin Templemore-Finlayson, Eugen Borcoci |
| 2000 | Generation of Realistic Signalling Traffic in an ISDN Load Test System using SDL User Models. | Thomas Steinert, Georg Rler |
| 2000 | Verification of a Sliding Window Protocol Using IOA and MONA. | Mark A. Smith, Nils Klarlund |
| 2000 | Compositionality for Improving Model Checking. | Antonella Santone |
| 2000 | From Refutation to Verification. | John M. Rushby |
| 2000 | Modeling Distributed Embedded Systems in Multiclock ESTEREL. | Basant Rajan, R. K. Shyamasundar |
| 2000 | Formal Verification of the TTP Group Membership Algorithm. | Holger Pfeifer |
| 2000 | On Test Derivation from Partial Specifications. | Alexandre Petrenko, Nina Yevtushenko |
| 2000 | Specification and Verification of Message Sequence Charts. | Doron A. Peled |