Reduced Latency IEEE Floating-Point Standard Adder Architectures.
Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, Cheng-Chew Lim
VenueCARITH
Year1999
ProceedingsIEEE Symposium on Computer Arithmetic
DBLP recordconf/arith/Beaumont-SmithBLL99 ↗
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