Skip to content
cs-conference-ranking
.org
By subfield
By rank
Methodology
⌕
Search 971 venues
Home
/
ASPDAC
/
Paper
The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance.
Jinsong Hou
,
Zeyi Wang
,
Xianlong Hong
Venue
B
ASPDAC
Year
1999
Proceedings
ASP-DAC
DBLP record
conf/aspdac/HouWH99 ↗
Browse the full
ASPDAC paper archive
.