| 2011 | ASPDAC | Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. | Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong |
| 2010 | ASPDAC | PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization. | Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong |
| 2010 | ASPDAC | Simultaneous slack budgeting and retiming for synchronous circuits optimization. | Shenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang |
| 2009 | ASPDAC | A novel thermal optimization flow using incremental floorplanning for 3D ICs. | Xin Li, Yuchun Ma, Xianlong Hong |
| 2009 | ASPDAC | Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. | Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong |
| 2009 | DATE | An efficient decoupling capacitance optimization using piecewise polynomial models. | Xiaoyi Wang, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Jacob Relles |
| 2009 | ISCAS | Buffer Planning for 3D ICs. | Sheqin Dong, Hongjie Bai, Xianlong Hong, Satoshi Goto |
| 2008 | ASPDAC | LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. | Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong |
| 2008 | ASPDAC | Vertical via design techniques for multi-layered P/G networks. | Shuai Li, Jin Shi, Yici Cai, Xianlong Hong |
| 2008 | ASPDAC | Symmetry constraint based on mismatch analysis for analog layout in SOI technology. | Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto |
| 2008 | ASPDAC | Heuristic power/ground network and floorplan co-design method. | Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong |
| 2008 | ASPDAC | Low power clock buffer planning methodology in F-D placement for large scale circuit design. | Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian |
| 2008 | DAC | Topological routing to maximize routability for package substrate. | Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong |
| 2008 | FPL | MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. | Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong |
| 2008 | ICCD | Gate planning during placement for gated clock network. | Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu |
| 2008 | ISCAS | Leakage power optimization for clock network using dual-Vth technology. | Weixiang Shen, Yici Cai, Xianlong Hong |
| 2007 | ASPDAC | DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. | Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, Xianlong Hong |
| 2007 | ASPDAC | Logic and Layout Aware Voltage Island Generation for Low Power Design. | Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong |
| 2007 | ASPDAC | Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach. | Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan |
| 2007 | ASPDAC | Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. | Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong |
| 2007 | ASPDAC | Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. | Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou |
| 2007 | ASPDAC | Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos. | Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang |
| 2007 | DATE | Statistical model order reduction for interconnect circuits considering spatial correlations. | Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong |
| 2007 | ICCAD | Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks. | Ning Mi, Sheldon X.-D. Tan, Pu Liu, Jian Cui, Yici Cai, Xianlong Hong |
| 2007 | ICCAD | 3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. | Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou |
| 2007 | ISCAS | Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building. | Yanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai |
| 2007 | ISCAS | Effective Acceleration of Iterative Slack Distribution Process. | Xinjie Wei, Yici Cai, Xianlong Hong |
| 2007 | ISCAS | Unified Quadratic Programming Approach For 3-D Mixed Mode Placement. | Haixia Yan, Zhuoyuan Li, Xianlong Hong, Qiang Zhou |
| 2007 | ISCAS | A Fast 3D-BSG Algorithm for 3D Packing Problem. | Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma |
| 2006 | ASPDAC | DraXRouter: global routing in X-Architecture with dynamic resource assignment. | Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, Guiying Yan |
| 2006 | ASPDAC | Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs. | Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong |
| 2006 | ASPDAC | Signal-path driven partition and placement for analog circuit. | Di Long, Xianlong Hong, Sheqin Dong |
| 2006 | ASPDAC | Efficient early stage resonance estimation techniques for C4 package. | Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong |
| 2006 | ASPDAC | CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model. | Yiyu Shi, Tong Jing, Lei He, Zhe Feng, Xianlong Hong |
| 2006 | ICCAD | Efficient process-hotspot detection using range pattern matching. | Hailong Yao, Subarna Sinha, Charles C. Chiang, Xianlong Hong, Yici Cai |
| 2006 | ISCAS | Buffer planning based on block exchanging. | Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen |
| 2006 | ISCAS | Floorplanning for 2.5-D system integration using multi-layer-BSG structure. | Sheqin Dong, Shuyi Zheng, Xianlong Hong |
| 2006 | ISCAS | A novel technique integrating buffer insertion into timing driven placement. | Lijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang |
| 2006 | ISCAS | High performance clock routing in X-architecture. | Weixiang Shen, Yici Cai, Jiang Hu, Xianlong Hong, Bing Lu |
| 2006 | ISCAS | Performance and power aware buffered tree construction. | Yibo Wang, Yici Cai, Xianlong Hong |
| 2006 | ISCAS | On handling the fixed-outline constraints of floorplanning using less flexibility first principles. | Shaojun Wei, Sheqin Dong, Xianlong Hong, Youliang Wu |
| 2006 | ISCAS | Congestion-driven W-shape multilevel full-chip routing framework. | Hailong Yao, Yici Cai, Xianlong Hong |
| 2006 | ISCAS | A novel low-power physical design methodology for MTCMOS. | Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong |
| 2005 | ASPDAC | Relaxed hierarchical power/ground grid analysis. | Yici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu |
| 2005 | ASPDAC | VLSI on-chip power/ground network optimization considering decap leakage currents. | Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan |
| 2005 | ASPDAC | Clock network minimization methodology based on incremental placement. | Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu |
| 2005 | ASPDAC | An-OARSMan: obstacle-avoiding routing tree construction with good length performance. | Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan |
| 2005 | ASPDAC | A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem. | Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong, Lei He |
| 2005 | ASPDAC | Register placement for low power clock network. | Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu |
| 2005 | ASPDAC | An improved P-admissible floorplan representation based on Corner Block List. | Renshen Wang, Sheqin Dong, Xianlong Hong |
| 2005 | ASPDAC | The polygonal contraction heuristic for rectilinear Steiner tree construction. | Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan |
| 2005 | ASPDAC | LFF algorithm for heterogeneous FPGA floorplanning. | Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu |
| 2005 | ASPDAC | Analysis of buffered hybrid structured clock networks. | Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan |
| 2005 | DAC | Partitioning-based approach to fast on-chip decap budgeting and minimization. | Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong |
| 2005 | DAC | Navigating registers in placement for clock network minimization. | Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu |
| 2005 | EUC | A New Buffer Planning Algorithm Based on Room Resizing. | Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen |
| 2005 | ICCSA | Multi-stage Detailed Placement Algorithm for Large-Scale Mixed-Mode Layout Design. | Lijuan Luo, Qiang Zhou, Xianlong Hong, Hanbin Zhou |
| 2005 | ICNC | A Hybrid Genetic Algorithm and Application to the Crosstalk Aware Track Assignment Problem. | Yici Cai, Bin Liu, Xiong Yan, Qiang Zhou, Xianlong Hong |
| 2005 | ISCAS | Integrated routing resource assignment for RLC crosstalk minimization. | Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong |
| 2005 | ISCAS | A global interconnect optimization algorithm under accurate delay model using solution space smoothing. | Yici Cai, Yibo Wang, Xianlong Hong |
| 2005 | ISCAS | VLSI block placement with alignment constraints based on corner block list. | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng |
| 2005 | ISCAS | A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. | Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani |
| 2005 | ISCAS | Fixed-outline floorplanning with constraints through instance augmentation. | Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani |
| 2005 | ISCAS | Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit. | Di Long, Xianlong Hong, Sheqin Dong |
| 2005 | ISCAS | Performance constrained floorplanning based on partial clustering [IC layout]. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng |
| 2005 | ISCAS | Interconnect delay optimization via high level re-synthesis after floorplanning. | Yunfeng Wang, Jinian Bian, Xianlong Hong |
| 2005 | ISCAS | Zero skew clock routing with tree topology construction using simulated annealing method. | Xinjie Wei, Yici Cai, Xianlong Hong |
| 2005 | ISCAS | Timing-driven global routing with efficient buffer insertion. | Jingyu Xu, Xianlong Hong, Tong Jing |
| 2005 | ISCAS | An efficient algorithm for buffered routing tree construction under fixed buffer locations with accurate delay models. | Yiqian Zhang, Xianlong Hong, Yici Cai |
| 2005 | ISCAS | A new approach based on LFF for optimization of dynamic hardware reconfigurations. | Zhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani |
| 2005 | VLSID | A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model. | Yibo Wang, Yici Cai, Xianlong Hong |
| 2004 | ASPDAC | A buffer planning algorithm with congestion optimization. | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2004 | ASPDAC | A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery. | Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan |
| 2004 | ASPDAC | Buffer allocation algorithm with consideration of routing congestion. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2004 | ASPDAC | A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design. | Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu |
| 2004 | ASPDAC | Efficient octilinear Steiner tree construction based on spanning graphs. | Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang |
| 2004 | ICCD | A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network. | Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan |
| 2004 | ISCAS | Module placement based on quadratic programming and rectangle packing using less flexibility first principle. | Sheqin Dong, Zhong Yang, Xianlong Hong, Yuliang Wu |
| 2004 | ISCAS | Partial random walk for large linear network analysis. | Weikun Guo, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong |
| 2004 | ISCAS | Layer assignment algorithm for RLC crosstalk minimization. | Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong |
| 2004 | ISCAS | Algorithm for yield driven correction of layout. | Yang Wang, Yici Cai, Xianlong Hong, Qiang Zhou |
| 2004 | ISCAS | Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration. | Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu |
| 2004 | ISCAS | Crosstalk driven routing resource assignment. | Hailong Yao, Qiang Zhou, Xianlong Hong, Yici Cai |
| 2004 | ISCAS | Performance and RLC crosstalk driven global routing. | Ling Zhang, Tong Jing, Xianlong Hong, Jingyu Xu, Jinjun Xiong, Lei He |
| 2004 | ISCAS | Shielding area optimization under the solution of interconnect crosstalk. | Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong, Lei He, Jinjun Xiong |
| 2004 | ISCAS | Quick and effective buffered legitimate skew clock routing. | Meng Zhao, Xinjie Wei, Yici Cai, Xianlong Hong |
| 2003 | ASPDAC | A buffer planning algorithm based on dead space redistribution. | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2003 | ASPDAC | VLSI module placement with pre-placed modules and considering congestion using solution space smoothing. | Sheqin Dong, Xianlong Hong, Xin Qi, Ruijie Wang, Song Chen, Jun Gu |
| 2003 | ASPDAC | A path-based timing-driven quadratic placement algorithm. | Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai |
| 2003 | ASPDAC | UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing. | Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Chung-Kuan Cheng, Jun Gu |
| 2003 | ASPDAC | Congestion driven incremental placement algorithm for standard cell layout. | Zhuoyuan Li, Weimin Wu, Xianlong Hong |
| 2003 | ASPDAC | BBE: hierarchical computation of 3-D interconnect capacitance with BEM block extraction. | Taotao Lu, Zeyi Wang, Xianlong Hong |
| 2003 | ASPDAC | A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design. | Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu |
| 2003 | DAC | Dynamic global buffer planning optimization based on detail block locating and congestion analysis. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2003 | ICCD | Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics. | Wenjian Yu, Zeyi Wang, Xianlong Hong |
| 2003 | ISCAS | Evaluating a bounded slice-line grid assignment in O(nlogn) time. | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2003 | ISCAS | Algorithms for analog VLSI 2D stack generation and block merging. | Rui Liu, Sheqin Dong, Xianlong Hong, Di Long, Jun Gu |
| 2003 | ISCAS | Combining clustering and partitioning in quadratic placement. | Yongqiang Lu, Xianlong Hong, Wenting Hou, Weimin Wu, Yici Cai |
| 2003 | ISCAS | Arbitrary convex and concave rectilinear block packing based on corner block list. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu |
| 2002 | ISCAS | A novel and efficient timing-driven global router for standard cell layout design based on critical network concept. | Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Jun Gu |
| 2002 | VLSID | A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI. | Shuzhou Fang, Zeyi Wang, Xianlong Hong |
| 2002 | VLSID | Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2002 | VLSID | An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing. | Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu |
| 2001 | ASPDAC | VLSI block placement using less flexibility first principles. | Sheqin Dong, Xianlong Hong, Youliang Wu, Yizhou Lin, Jun Gu |
| 2001 | ASPDAC | A new congestion-driven placement algorithm based on cell inflation. | Wenting Hou, Hong Yu, Xianlong Hong, Yici Cai, Weimin Wu, Jun Gu, William H. Kao |
| 2001 | ASPDAC | VLSI floorplanning with boundary constraints based on corner block list. | Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2001 | DAC | Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2001 | ICCAD | Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques. | Xiaohai Wu, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai |
| 2000 | ASPDAC | A simplified hybrid method for calculating the frequency-dependent inductances of transmission lines with rectangular cross section. | Shuzhou Fang, Xiaobo Tang, Zeyi Wang, Xianlong Hong |
| 2000 | ASPDAC | Hierarchical computation of 3-D interconnect capacitance using direct boundary element method. | Jiangchun Gu, Zeyi Wang, Xianlong Hong |
| 2000 | ASPDAC | Area routing oriented hierarchical corner stitching with partial bin. | Yan Zhang, Baohua Wang, Yici Cai, Xianlong Hong |
| 2000 | ASPDAC | MMP: a novel placement algorithm for combined macro block and standard cell layout design. | Hong Yu, Xianlong Hong, Yici Cai |
| 2000 | ICCAD | Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. | Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu |
| 1999 | ASPDAC | A New Global Routing Algorithm Independent Of Net Ordering. | Haiyun Bao, Xianlong Hong, Yici Cai |
| 1999 | ASPDAC | FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking. | Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong |
| 1999 | ASPDAC | The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance. | Jinsong Hou, Zeyi Wang, Xianlong Hong |
| 1999 | ASPDAC | A Timing-Driven Block Placer Based on Sequence Pair Model. | Gang Huang, Xianlong Hong, Changge Qiao, Yici Cai |
| 1999 | ASPDAC | Design and Optimization of Power/Ground Network for Cell-Based VLSIs with Macro Cells. | Xiaohai Wu, Changge Qiao, Xianlong Hong |
| 1997 | ASPDAC | VEAP: Global optimization based efficient algorithm for VLSI placement. | Tianming Kong, Xianlong Hong, Changge Qiao |
| 1993 | DAC | Performance-Driven Steiner Tree Algorithm for Global Routing. | Xianlong Hong, Tianxiong Xue, Ernest S. Kuh, Chung-Kuan Cheng, Jin Huang |
| 1993 | DAC | An Efficient Timing-Driven Global Routing Algorithm. | Jin Huang, Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh |
| 1992 | DAC | FARM: An Efficient Feed-Through Pin Assignment Algorithm. | Xianlong Hong, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh |