Symmetry constraint based on mismatch analysis for analog layout in SOI technology.
Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto
Browse the full ASPDAC paper archive.
Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto
Browse the full ASPDAC paper archive.