| 2018 | ISCAS | Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips. | Fengxian Jiao, Sheqin Dong, Bei Yu, Bing Li, Ulf Schlichtmann |
| 2016 | ASPDAC | Ordered Escape routing for grid pin array based on Min-cost Multi-commodity Flow. | Fengxian Jiao, Sheqin Dong |
| 2014 | ISCAS | Post-floorplanning power optimization for MSV-driven application specific NoC design. | Kan Wang, Sheqin Dong |
| 2013 | ASPDAC | Power optimization for application-specific 3D network-on-chip with multiple supply voltages. | Kan Wang, Sheqin Dong |
| 2012 | ASPDAC | Linear optimal one-sided single-detour algorithm for untangling twisted bus. | Tao Lin, Sheqin Dong, Song Chen, Satoshi Goto |
| 2011 | ASPDAC | Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. | Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong |
| 2011 | ASPDAC | Network flow-based simultaneous retiming and slack budgeting for low power design. | Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto |
| 2010 | ASPDAC | Floorplanning and topology generation for application-specific network-on-chip. | Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto |
| 2009 | ISCAS | Buffer Planning for 3D ICs. | Sheqin Dong, Hongjie Bai, Xianlong Hong, Satoshi Goto |
| 2008 | ASPDAC | LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. | Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong |
| 2008 | ASPDAC | Symmetry constraint based on mismatch analysis for analog layout in SOI technology. | Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto |
| 2008 | CSCWD | Cache miss reduction through hardware-assisted loop optimization. | Kang Zhao, Jinian Bian, Chenqian Jiang, Sheqin Dong, Satoshi Goto |
| 2008 | ICCAD | A novel fixed-outline floorplanner with zero deadspace for hierarchical design. | Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng |
| 2007 | ASPDAC | Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. | Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong |
| 2007 | ASPDAC | Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. | Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou |
| 2007 | CSCWD | A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design. | Kang Zhao, Jinian Bian, Sheqin Dong |
| 2007 | ISCAS | A Fast 3D-BSG Algorithm for 3D Packing Problem. | Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma |
| 2006 | ASPDAC | Signal-path driven partition and placement for analog circuit. | Di Long, Xianlong Hong, Sheqin Dong |
| 2006 | ISCAS | Buffer planning based on block exchanging. | Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen |
| 2006 | ISCAS | Floorplanning for 2.5-D system integration using multi-layer-BSG structure. | Sheqin Dong, Shuyi Zheng, Xianlong Hong |
| 2006 | ISCAS | On handling the fixed-outline constraints of floorplanning using less flexibility first principles. | Shaojun Wei, Sheqin Dong, Xianlong Hong, Youliang Wu |
| 2005 | ASPDAC | An improved P-admissible floorplan representation based on Corner Block List. | Renshen Wang, Sheqin Dong, Xianlong Hong |
| 2005 | ASPDAC | LFF algorithm for heterogeneous FPGA floorplanning. | Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu |
| 2005 | EUC | A New Buffer Planning Algorithm Based on Room Resizing. | Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen |
| 2005 | ISCAS | VLSI block placement with alignment constraints based on corner block list. | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng |
| 2005 | ISCAS | Fixed-outline floorplanning with constraints through instance augmentation. | Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani |
| 2005 | ISCAS | Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit. | Di Long, Xianlong Hong, Sheqin Dong |
| 2005 | ISCAS | Performance constrained floorplanning based on partial clustering [IC layout]. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng |
| 2005 | ISCAS | A new approach based on LFF for optimization of dynamic hardware reconfigurations. | Zhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani |
| 2004 | ASPDAC | A buffer planning algorithm with congestion optimization. | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2004 | ASPDAC | Buffer allocation algorithm with consideration of routing congestion. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2004 | ISCAS | Module placement based on quadratic programming and rectangle packing using less flexibility first principle. | Sheqin Dong, Zhong Yang, Xianlong Hong, Yuliang Wu |
| 2003 | ASPDAC | A buffer planning algorithm based on dead space redistribution. | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2003 | ASPDAC | VLSI module placement with pre-placed modules and considering congestion using solution space smoothing. | Sheqin Dong, Xianlong Hong, Xin Qi, Ruijie Wang, Song Chen, Jun Gu |
| 2003 | DAC | Dynamic global buffer planning optimization based on detail block locating and congestion analysis. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2003 | ISCAS | Evaluating a bounded slice-line grid assignment in O(nlogn) time. | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2003 | ISCAS | Algorithms for analog VLSI 2D stack generation and block merging. | Rui Liu, Sheqin Dong, Xianlong Hong, Di Long, Jun Gu |
| 2003 | ISCAS | Arbitrary convex and concave rectilinear block packing based on corner block list. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu |
| 2002 | VLSID | Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2001 | ASPDAC | VLSI block placement using less flexibility first principles. | Sheqin Dong, Xianlong Hong, Youliang Wu, Yizhou Lin, Jun Gu |
| 2001 | ASPDAC | VLSI floorplanning with boundary constraints based on corner block list. | Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2001 | DAC | Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2000 | ICCAD | Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. | Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu |